DATASHEET T1/E1 CLOCK MULTIPLIER ICS548-05 Description Features The ICS548-05 is a low-cost, low-jitter, Packaged in 16-pin TSSOP high-performace clock synthesizer designed to Available in Pb (lead) free package produce x16 and x24 clocks from T1 and E1 Ideal for telecom/datacom chips frequencies. Using IDTs patented analog/digital Replaces oscillators Phase- Locked Loop (PLL) techniques, the device uses 3.3 V or 5 V operation a crystal or clock input to synthesize popular Uses a crystal or clock input communications frequencies. Power down modes allow the chip to turn off completely, or the PLL and clock Produces 24.704, 37.056, 32.768, or 49.152 MHz output to be turned off separately. Includes Power-down features Advanced, low-power, sub-micron CMOS process IDT manuafactures the largest variety of communications clock synthesizers for all applications. See also the MK2049-34 for generating Consult IDT to eliminate VCXOs, crystals, and Industrial temperature range available oscillators from your board. Block Diagram MSEL X16 or x24 REFEN PLL/Clock Synthesis CLK PDCLK Circuitry 1.544 MHz or X1/ICLK Input 2.048 MHz Buffer/ clock or crystal Crystal input REFOUT Oscillator X2 Optional crystal capacitors IDT T1/E1 CLOCK MULTIPLIER 1 ICS548-05 REV D 091511ICS548-05 T1/E1 CLOCK MULTIPLIER CLOCK SYNTHESIZER Output Clock Selection Table Pin Assignment MSEL Input (MHz) CLK (MHz) 1 X1/ICLK 16 X2 Pin 13 PIns 1, (16) PIn 9 2 VDD 15 DC 0 1.544 24.704 VDD 3 14 REFOUT 1 1.544 37.056 REFEN 4 13 MSEL 0 2.048 32.768 GND 5 12 GND 1 2.048 49.152 GND 6 11 PDCLK Power Down Clock Selection Table GND 7 10 DC REFEN PDCLK Power Down Selection Mode VDD 8 9 CLK Pin 4 PIn 11 0 0 The entire chip is off. 16-pin TSSOP 0 1 PLL and clock output run, REFOUT low. 1 0 REFOUT running, PLL off, CLK low. 1 1 All running. Key: 0 = connect directly to GND 1 = connect directly to VDD Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 X1/ICLK XI Crystal connection. Connect this pin to a crystal or clock input. 2, 3, 8 VDD Power Connect to +3.3 V or +5 V. All VDDs must be the same. 4 REFEN Input Reference Clock Enable. See table above. Connect to GND for best jitter/phase noise. 5, 6, 7, 12 GND Power Connect to ground. 9 CLK Output Clock output set by input status of MSEL. See table above. 10, 15 DC Dont Connect. Do not connect these pins to anything. 11 PDCLK Input Power down clock. See table above. 13 MSEL Input Multiplier select pin. Selects x16 when low, x24 when high. 14 REFOUT Output Buffered reference output clock. Controlled by REFEN. 16 X2 XO Crystal connection. Connect this pin to a crystal or leave unconnected for a clock. Key: XI, XO = crystal connections the in put pin MSEL must be tied directly to VDD or GND. For a clock input, connect the input X1 and leave X2 unconnected (floating). IDT T1/E1 CLOCK MULTIPLIER 2 ICS548-05 REV D 091511