551SPGGI Renesas

Datasheet 551S Low Skew 1 to 4 Clock Buffer The 551S is a low cost, high-speed single input to Features four output clock buffer with best in class additive Low additive phase jitter RMS: 50fs phase jitter of sub 50fsec. Extremely low skew outputs (50ps) Renesas makes many non-PLL and PLL based low Low cost clock buffer skew output devices as well as Zero Delay Buffers to Packaged in 8-SOIC, 8-TSSOP and 8-DFN synchronize clocks. Contact Renesas for all of your Input/output clock frequency up to 200MHz clocking needs. Non-inverting output clock Ideal for networking clocks Operating voltages: 1.8V to 3.3V Output Enable mode tri-states outputs Advanced, low power CMOS process Extended temperature range (-40C to +105C) Block Diagram Q1 Q2 ICLK Q3 Q4 Output Enable Figure 1. Block Diagram X0006813 Rev.1.3 Page 1 Mar 12, 2021 2021 Renesas Electronics551S Datasheet Contents 1. Pin Information 3 1.1 Pin Assignments . 3 1.2 Pin Descriptions . 3 1.3 External Components . 3 2. Specifications . 4 2.1 Absolute Maximum Ratings . 4 2.2 Recommended Operating Conditions . 4 2.3 Thermal Specifications 4 2.4 Electrical Specifications 5 2.4.1 DC Electrical Characteristics 5 2.4.2 AC Electrical Characteristics . 6 2.5 Phase Noise Plots 8 2.6 Test Load and Circuit 9 3. Package Outline Drawings . 9 4. Marking Diagrams 9 5. Ordering Information . 10 6. Revision History 10 X0006813 Rev.1.3 Page 2 Mar 12, 2021