557M-01LF Renesas

DATASHEET PCI-EXPRESS GEN1 CLOCK SOURCE ICS557-01 Description Features TM The ICS557-01 is a clock chip designed for use in Supports PCI-Express HCSL Outputs 0.7 V current mode differential pair PCI-Express Cards as a clock source. It provides a pair of differential outputs at 100 MHz in a small 8-pin SOIC Supports LVDS Output Levels package. Packaged in 8-pin SOIC RoHS 5 (green) or RoHS 6 (green and lead free) Using IDTs patented Phase-Locked Loop (PLL) compliant packaging techniques, the device takes a 25 MHz crystal input and Operating voltage of 3.3 V produces HCSL (Host Clock Signal Level) differential outputs at 100 MHz clock frequency. LVDS signal levels can Low power consumption also be supported via an alternative termination scheme. Input frequency of 25 MHz Short term jitter 100 ps (peak-to-peak) Output Enable via pin selection Industrial temperature range available For PCIe Gen2 applications, see the 5V41064 For PCIe Gen3 applications, see the 5V41234 Block Diagram VDD CLK Phase Lock Loop CLK X1 Clock Buffer/ 25 MHz Crystal crystal /clock Oscillator X2 Crystal Tuning Capacitors R (IREF) R GND OE IDT PCI-EXPRESS GEN1 CLOCK SOURCE 1 ICS557-01 REV P 072512ICS557-01 PCI-EXPRESS GEN1 CLOCK SOURCE PCIE Pin Assignment 1 8 VDD OE 2 7 CLK X1 3 6 X2 CLK GND 4 5 IREF 8 Pin (150 mil) SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 OE Input Output Enable signal (H = outputs are enabled, L = outputs are disabled/tristated). Internal pull-up resistor. 2 X1 Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock. 3 X2 XO Crystal Connection. Connect to a parallel mode crystal. Leave floating if clock input. 4 GND Power Connect to ground. 5 IREF Output A 475 precision resistor connected between this pin and ground establishes the external reference current. 6 CLK Output HCSL differential complementary clock output. 7 CLK Output HCSL differential clock output. 8 VDD Power Connect to +3.3 V. IDT PCI-EXPRESS GEN1 CLOCK SOURCE 2 ICS557-01 REV P 072512