VersaClock 3S Programmable 5L35021 Clock Generator Datasheet Description Features The 5L35021 is a member of the VersaClock 3S programmable Configurable OE pin function as OE, PD , PPS or DFC control clock generator family with 1.8V operation voltage, and is function designed for industrial, consumer, and PCI Express applications. Configurable PLL bandwidth minimizes jitter peaking The device features a 3 PLL architecture design each PLL is PPS: Proactive Power Saving features save power during the individually programmable and allowing up to 6 unique frequency end device power down mode outputs. PPB: Performance Power Balancing feature allows minimum The 5L35021 has built-in features such as Proactive Power power consumption based on required performance Saving (PPS), Performance-Power Balancing (PPB), Overshoot DFC: Dynamic Frequency Control feature allows user to Reduction Technology (ORT) and extreme low power DCO. An dynamically switch between and up to 4 different frequencies internal OTP memory allows the user to store the configuration in smoothly the device without programming after power up, then program the 2 Spread spectrum clock to lower system EMI 5L35021 again through the I C interface. 2 I C interface The device has programmable VCO and PLL source selection, Suspend Mode, featuring RTC clock only when system goes allowing power-performance optimization based on the application into low-power operation modes requirements. Output Features Typical Applications 2 DIFF outputs with configurable LPHSCL, LVCMOS output Embedded computing devices pairs: 1MHz250MHz (125MHz with LVCMOS mode) Consumer application crystal replacements 1 LVCMOS output: 1MHz125MHz SmartDevice, Handheld, and Consumer applications LVPECL, LVDS, CML and SSTL logic can be easily supported with the LP-HCSL outputs. See application note AN-891 for Key Specifications alternate terminations PCIe Gen1/2/3 compliant Maximum of 5 LVCMOS outputs as REF + 3 SE + 2 Typical 1.5ps rms jitter integer range: 12kHz20MHz DIFF T/C as LVCMOS Typical ultra-power-down current 50 A Low-power 32.768kHz clock supported for SE1 output < 2 A RTC clock in Suspend Mode operation Block Diagram CLKIN/X1 OSC X2 VDDDIFF 1 Programmable DIFF1 Load Capacitor DIFF1B PLL1 VDDDIFF 2 SEL DFC/ SCL DFC1 Mux DIFF2 SDA DFC0 & PLL2 DIFF2B Divider Calibration VDDSE1 VDD18 SE1 PLL3 VDDA OE1 32.768K DCO VBAT 2019 Integrated Device Technology, Inc. 1 October 4, 20195L35021 Datasheet Pin Assignments Figure 1. Pin Assignments for 3 x 3 mm 20-VFQFPN Package Top View 19 18 17 16 20 1 15 VDDA DIFF1 2 14 SDA DFCO DIFF1B 13 3 5L35021 SEL DFC/SCL DFC1 VDDDIFF1 4 12 CLKIN/X2 OE1 5 11 CLKINB/X1 SE1 67 8 9 10 3 x 3 mm 20-QFN Pin Descriptions Table 1. Pin Descriptions Number Name Type Description 1V Power V 1.8V DDA DD 2 2SDA DFC0 I/O I C data pin. The pin can be DFC0 function by pin 3 SEL DFC power-on latch status. 2 I C CLK pin. SEL DFC/ SEL DFC is a latch input pin during the power-up. 3 Input 2 SCL DFC1 High on power-on: I C mode as SCLK function. Low on power-on: pin 3 SCL and pin 2 SDA as DFC function control pins. 4 CLKIN/X2 I/O Crystal oscillator interface output or differential clock input pin (CLKIN). 5 CLKINB/X1 Input Crystal oscillator interface input or differential clock input pin (CLKINB). 6V Power Power supply pin for 32.768kHz DCO usually connect to coin cell battery, 1.8V. BAT 7V Power Connect to ground. SS 8V Power V 1.8V. DD18 DD 9V Power Connect to ground. SSSE1 10 V Power Output power supply. Connect to 1.8V. Sets output voltage levels for SE1. DDSE1 11 SE1 Output Output clock SE1. OE1s function selected from OTP pre-programmed register bits. 12 OE1 Input OE1 pull to 6.5V when burn OTP registers. Refer to OE Pin Functions table for details. 13 V Power Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF1. DDDIFF1 2019 Integrated Device Technology, Inc. 2 October 4, 2019 VBAT VSSDIFF2 VSS DIFF2 VDD18 DIFF2B VSSSE1 VDDDIFF2 VDDSE1 VSSDIFF1