VersaClock 3S Programmable 5L35023 Clock Generator Datasheet Description Features The 5L35023 is a member of the VersaClock 3S programmable Configurable OE pin function as OE, PD , PPS or DFC control clock generator family with 1.8V operation voltage, and is function designed for industrial, consumer, and PCI Express applications. Configurable PLL bandwidth minimizes jitter peaking The device features a 3 PLL architecture design each PLL is PPS: Proactive Power Saving features save power during the individually programmable and allowing up to 6 unique frequency end device power down mode outputs. PPB: Performance Power Balancing feature allows minimum The 5L35023 has built-in features such as Proactive Power power consumption based on required performance Saving (PPS), Performance-Power Balancing (PPB), Overshoot DFC: Dynamic Frequency Control feature allows user to Reduction Technology (ORT) and extreme low power DCO. An dynamically switch between and up to 4 different frequencies internal OTP memory allows the user to store the configuration in smoothly the device without programming after power-up, then program the 2 Spread spectrum clock to lower system EMI 5L35023 again through the I C interface. 2 I C interface The device has programmable VCO and PLL source selection, Suspend Mode, featuring RTC clock only when system goes allowing power-performance optimization based on the application into low-power operation modes requirements. Output Features Typical Applications 2 DIFF outputs with configurable LPHSCL, LVCMOS output Embedded computing devices pairs: 1MHz125MHz Consumer application crystal oscillator replacements 3 LVCMOS outputs: 1MHz125MHz SmartDevice, Handheld, and Consumer applications LVPECL, LVDS, CML and SSTL logic can be easily supported with the LP-HCSL outputs. See application note AN-891 for Key Specifications alternate terminations PCIe Gen1/2/3 compliant Maximum of 8 LVCMOS outputs Typical 1.5ps rms jitter integer range: 12kHz20MHz Low-power 32.768kHz clock supported for all SE1SE3 Typical ultra-power-down current 50 A < 2 A RTC clock in Suspend Mode operation Block Diagram CLKIN/X1 REF OSC X2 VDDDIFF1 DIFF1 Programmable Load Capacitor DIFF1B PLL1 VDDDIFF2 SEL DFC/ SCL DFC1 DIFF2 SDA DFC0 DIFF2B VDDSE1 Mux PLL2 SE1 & Divider OE1 Calibration VDDSE2 SE2 PLL3 VDD18 OE2 32.768K VDDA VDDSE3 DCO SE3 VBAT OE3 2019 Integrated Device Technology, Inc. 1 October 4, 20195L35023 Datasheet Pin Assignments Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package Top View 24 23 22 21 20 19 1 18 VDDA DIFF1 2 17 SDA DFCO DIFF1B 16 3 SEL DFC/SCL DFC1 VDDDIFF1 5L35023 15 X2 4 OE1 5 14 CLKIN/X1 SE1 6 13 VBAT VDDSE1 7 8 9 101112 4 x 4 mm 24-VFQFPN Pin Descriptions Table 1. Pin Descriptions Number Name Type Description 1V Power V 1.8V. DDA DD 2 2SDA DFC0 I/O I C DATA pin, the pin can be DFC0 function by pin 3 SEL DFC power on latch status. 2 I C CLK pin, SEL DFC is a latch input pin during the power-up. SEL DFC/ 2 3 Input High on power-on: I C mode as SCLK function. SCL DFC1 Low on power-on: pin 3 SCL and pin 2 SDA as DFC function control pins. 4 X2 I/O Crystal oscillator interface output. 5 CLKIN/X1 Input Crystal oscillator interface input or single-ended clock input pin (CLKIN). 6V Power Power supply pin for 32.768kHz DCO usually connect to coin cell battery, 1.8V. BAT 7 NC No connection. 8 REF Output 1.8V reference clock output. 9V Power V 1.8V. DD18 DD 10 OE2 Input Output enable control 2, multi-function pin. Refer to OE function table. 11 V Power Output power supply. Connect to 1.8V. Sets output voltage levels for SE2. DDSE2 12 SE2 Output Output clock SE2. 13 V Power Output power supply. Connect to 1.8V. Sets output voltage levels for SE1. DDSE1 2019 Integrated Device Technology, Inc. 2 October 4, 2019 NC DIFF2 REF DIFF2B VDD18 VDDDIFF2 OE2 OE3 VDDSE2 VDDSE3 SE2 SE3