VersaClock Programmable Clock 5P35023 Datasheet Generator Description Features Configurable OE pin function as OE, PD , PPS or DFC control The 5P35023 is a VersaClock programmable clock generator and function is designed for low-power, consumer, and high-performance PCI Express applications. The 5P35023 device is a three PLL Configurable PLL bandwidth minimizes jitter peaking architecture design, and each PLL is individually programmable PPS: Proactive Power Saving features save power during the and allowing for up to six unique frequency outputs. end device power down mode The 5P35023 has built-in unique features such as Proactive PPB: Performance Power Balancing feature allows minimum Power Saving (PPS), Performance-Power Balancing (PPB), power consumption based on required performance Overshot Reduction Technology (ORT) and Extreme Low Power DFC: Dynamic Frequency Control feature allows user to DCO. An internal OTP memory allows the user to store the dynamically switch between and up to 4 different frequencies configuration in the device. After power up, the user can change smoothly the device register settings through the I2C interface when I2C Two PLLs support independent spread spectrum clocks to mode is selected. lower system EMI The device has programmable VCO and PLL source selection to Store user configuration into OTP memory allow the user to do power-performance optimization based on the 2 I C interface application requirements. It also supports three single-ended Available in Automotive Grade 2 (-40C to +105C) or outputs and two pair of differential outputs that support LVCMOS, industrial (-40 to +85) temperature ranges LVPECL, LVDS and LP-HCSL. A Low Power 32.768kHz clock is supported with only less than 2A current consumption for system RTC reference clock. Output Features 2 DIFF outputs with configurable LP-HSCL, LVDS, LVPECL, Typical Applications LVCMOS output pairs. 1MHz500MHz (160MHz with LVCMOS mode) PCIe Gen13 clock generator 3 LVCMOS outputs: 1MHz160MHz Consumer application crystal replacements Maximum 8 LVCMOS outputs as REF + 3 SE + 2 DIFF T/C SmartDevice, Handheld as LVCMOS Computing and consumer applications Low power 32.768kHz clock supported for all SE1SE3 Automotive applications (infotainment, dashboard, camera/vision, computing, networking) Key Specifications PCIe clocks phase jitter: PCIe Gen3 Differential clocks < 1.5ps rms jitter integer range 12kHz 20MHz 2019 Integrated Device Technology, Inc. 1 October 4, 20195P35023 Datasheet Contents Description 1 Typical Applications . 1 Key Specifications 1 Features 1 Output Features 1 Block Diagram . 3 Pin Assignments 3 Pin Descriptions 4 Power Group 5 Output Sources 5 Device Features and Functions 7 DFC Dynamic Frequency Control 7 DFC Function Programming 7 PPS Proactive Power Saving Function 8 PPS Function Programming 9 Timer Function Description . 9 OE Pin Function . 9 Reference Input and Selection . 10 Crystal Input (X1/X2) 10 Spread Spectrum . 11 Analog Spread Spectrum . 11 Digital Spread Spectrum 12 VBAT . 12 ORTVCO Overshoot Reduction Technology . 13 PLL Features and Descriptions . 13 Output Clock Test Conditions . 14 Absolute Maximum Ratings 15 Recommended Operating Conditions 15 Electrical Characteristics 16 AC Electrical Characteristics . 24 PCI Express Jitter Specifications 26 Spread Spectrum Generation Specifications . 26 I2C Bus Characteristics . 27 I2C Mode Operations . 27 Glossary of Features . 41 Package Outline Drawings . 41 Marking Diagrams (industrial) 41 Marking Diagrams (automotive) . 42 Ordering Information . 42 Revision History . 43 2019 Integrated Device Technology, Inc. 2 October 4, 2019