5P49EE502NDGI Renesas

DATASHEET VERSACLOCK LOW POWER CLOCK GENERATOR IDT5P49EE502 Description Features The IDT5P49EE502 is a programmable clock generator Four internal PLLs intended for low power, battery operated consumer Internal non-volatile EEPROM applications. There are four internal PLLs, each individually 2 Internal I C EEPROM master interface programmable, allowing for up to five differrent output 2 frequencies. The frequencies are generated from a single FAST (400kHz) mode I C serial interfaces reference clock. The reference clock can come from either Input Frequencies a TCXO or fundamental mode crystal. TCXO: 10 MHz to 40 MHz Crystal: 8 MHz to 30 MHz The IDT5P49EE502 can be programmed through the use 2 of the I C interfaces. The programming interface enables Output Frequency Ranges: kHz to 120 MHz the device to be programmed when it is in normal operation Each PLL has an 8-bit reference divider and a 11-bit or what is commonly known as in system programmable. feedback-divider An internal EEPROM allows the user to save and restore 8-bit output-divider blocks the configuration of the device without having to reprogram it on power-up. One of the PLLs support Spread Spectrum generation capable of configuration to pixel rate, with adjustable Each of the four PLLs has an 8-bit reference divider and a modulation rate and amplitude to support video clock 11-bit feedback divider. This allows the user to generate with no visible artifacts four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the I/O Standards: PLL response to the application. For instance, the user can Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS tune the PLL parameters to minimize jitter generation or to 2 independent adjustable VDDO groups. maximize jitter attenuation. Spread spectrum generation is Programmable Slew Rate Control supported on one of the PLLs. Programmable Loop Bandwidth Settings Spread spectrum generation is supported on one of the PLLs. The device is specifically designed to work with Programmable output inversion to reduce bimodal jitter display applications to ensure that the spread profile Individual output enable/disable remains consistent for each HSYNC in order to reduce Power-down/Sleep mode ROW noise. It also may operate in standard spread 10A max in power down mode spectrum mode. 1.8V VDD Core Voltage There are total five 8-bit output dividers. The outputs are connected to the PLLs via the switch matrix. The switch Available in 20pin 3x3mm QFN packages matrix allows the user to route the PLL outputs to any -40 to +85 C Industrial Temp operation output bank. This feature can be used to simplify and optimize the board layout. In addition, each output s slew rate and enable/disable function can be programmed. Target Applications Smart Mobile Handset Personal Navigation Device (PND) Camcorder DSC Portable Game Console Personal Media Player IDT VERSACLOCK LOW POWER CLOCK GENERATOR 1 IDT5P49EE502 REV L 111714IDT5P49EE502 VERSACLOCK LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Functional Block Diagram VDD VDDO1 VDDO2 S R /DIV0 OUT0 C 0 XIN/REF S R PLLA /DIV1 OUT1 XOUT C 1 S R /DIV2 OUT2 C PLLB(SS) 2 SDA Control S Logic SCL /DIV3 OUT3 R C 3 SEL PLLC S /DIV4 OUT4 R C 4 PLLD GND IDT VERSACLOCK LOW POWER CLOCK GENERATOR 2 IDT5P49EE502 REV L 111714