Programmable Clock Generator 5P49V5901 DATASHEET Description Features The 5P49V5901 is a programmable clock generator intended Generates up to four independent output frequencies for high performance consumer, networking, industrial, High performance, low phase noise PLL, <0.7 ps RMS computing, and data-communications applications. typical phase jitter on outputs: Configurations may be stored in on-chip One-Time 2 PCIe Gen1, 2, 3 compliant clock capability Programmable (OTP) memory or changed using I C USB 3.0 compliant clock capability interface. This is IDTs fifth generation of programmable clock technology (VersaClock 5). 1 GbE and 10 GbE The frequencies are generated from a single reference clock. Four fractional output dividers (FODs) The reference clock can come from one of the two redundant Independent Spread Spectrum capability on each output clock inputs. A glitchless manual switchover function allows pair one of the redundant clocks to be selected during normal Four banks of internal non-volatile in-system operation. programmable or factory programmable OTP memory Two select pins allow up to 4 different configurations to be 2 I C serial programming interface programmed and accessible using processor GPIOs or One reference LVCMOS output clock bootstrapping. The different selections may be used for different operating modes (full function, partial function, partial Four universal output pairs: power-down), regional standards (US, Japan, Europe) or Each configurable as one differential output pair or two system production margin testing. LVCMOS outputs 2 The device may be configured to use one of two I C I/O Standards: addresses to allow multiple devices to be used in a system. Single-ended I/Os: 1.8V to 3.3V LVCMOS Differential I/Os - LVPECL, LVDS and HCSL Pin Assignment Input frequency ranges: LVCMOS Reference Clock Input (XIN/REF) 1MHz to 200MHz LVDS, LVPECL, HCSL Differential Clock Input (CLKIN, CLKINB) 1MHz to 350MHz Crystal frequency range: 8MHz to 40MHz Output frequency ranges: LVCMOS Clock Outputs 1MHz to 200MHz 24 23 22 21 20 19 1 18 V 2 DDO LVDS, LVPECL, HCSL Differential Clock Outputs CLKIN 1MHz to 350MHz 2 17 OUT2 CLKINB Individually selectable output voltage (1.8V, 2.5V, 3.3V) for XOUT 3 16 OUT2B EPAD each output pair 4 XIN/REF 15 V 3 DDO Redundant clock inputs with manual switchover 5 14 V OUT3 DDA Programmable loop bandwidth 6 13 OUT3B CLKSEL 8 7 9 10 11 12 Programmable output to output skew Programmable slew rate control Programmable crystal load capacitance Individual output enable/disable Power-down mode 1.8V, 2.5V or 3.3V core V , V DDD DDA 24-pin VFQFPN Available in 24-pin VFQFPN 4mm x 4mm package -40 to +85C industrial temperature operation 5P49V5901 FEBRUARY 21, 2019 1 2019 Integrated Device Technology, Inc. SD/OE OUT0 SEL I2CB V 0 SEL1/SDA DDO SEL0/SCL V DDD V 4 V 1 DDO DDO OUT1 OUT4 OUT1B OUT4B5P49V5901 DATASHEET Functional Block Diagram V 0 DDO XIN/REF OUT0 SEL I2CB XOUT V 1 DDO OUT1 FOD1 OUT1B CLKIN V 2 DDO CLKINB OUT2 FOD2 OUT2B CLKSEL PLL V 3 DDO SD/OE OUT3 FOD3 OUT3B SEL1/SDA 4 V DDO OTP and SEL0/SCL OUT4 Control Logic FOD4 OUT4B V DDA V DDD Applications Ethernet switch/router PCI Express 1.0/2.0/3.0 Broadcast video/audio timing Multi-function printer Processor and FPGA clocking Any-frequency clock conversion MSAN/DSLAM/PON Fiber Channel, SAN Telecom line cards 1 GbE and 10 GbE PROGRAMMABLE CLOCK GENERATOR 2 FEBRUARY 21, 2019