Programmable Clock Generator 5P49V5907 DATASHEET Description Features The 5P49V5907 is a programmable clock generator intended Generates up to four independent output frequencies with a for high performance consumer, networking, industrial, total of 7 differential outputs and one reference output computing, and data-communications applications. Supports multiple differential output I/O standards: Configurations may be stored in on-chip One-Time Three universal outputs pairs with each configurable 2 Programmable (OTP) memory or changed using I C as one differential output pair (LVDS, LVPECL or interface. This is IDTs fifth generation of programmable clock regular HCSL) or two LVCMOS outputs. Frequency of technology (VersaClock 5). each output pair can be individually programmed The frequencies are generated from a single reference clock Four copies of Low Power HCSL(LP-HCSL) outputs. or crystal. Two select pins allow up to 4 different Programmable frequency: configurations to be programmed and accessible using See Output Features and Descriptions for details processor GPIOs or bootstrapping. The different selections may be used for different operating modes (full function, One reference LVCMOS output clock partial function, partial power-down), regional standards (US, High performance, low phase noise PLL, <0.7 ps RMS Japan, Europe) or system production margin testing. typical phase jitter on outputs: 2 The device may be configured to use one of two I C PCIe Gen1, 2, 3 compliant clock capability addresses to allow multiple devices to be used in a system. USB 3.0 compliant clock capability 1 GbE and 10 GbE Pin Assignment Four fractional output dividers (FODs) Independent Spread Spectrum capability from each fractional output divider (FOD) Four banks of internal non-volatile in-system programmable or factory programmable OTP memory 2 I C serial programming interface Input frequency ranges: 40 39 38 37 36 35 34 33 32 31 LVCMOS Reference Clock Input (XIN/REF) 1MHz 1 V 2 30 DDO NC to 200MHz OUT2 2 29 XOUT Crystal frequency range: 8MHz to 40MHz OUT2B XIN/REF 3 28 Output frequency ranges: V 4 DDA 27 V DD LVCMOS Clock Outputs 1MHz to 200MHz 5 V 26 DDO V DD EPAD 6 LP-HCSL Clock Outputs 1MHz to 200MHz 25 V DD CORE OUT7 7 24 OUT7B OUT3 Other Differential Clock Outputs 1MHz to 350MHz OUT6 8 23 OUT3B Programmable loop bandwidth 22 9 NC OUT6B Programmable crystal load capacitance 10 21 NC SD/OE Power-down mode 11 12 13 14 15 16 17 18 19 20 Mixed voltage operation: 1.8V core 1.8V VDDO for 4 LP-HCSL outputs 1.8V to 3.3V VDDO for other outputs (3 programmable differential outputs and 1 reference output) 40-pin VFQFPN See Pin Descriptions for details Packaged in 40-pin 5mm x 5mm VFQFPN (NDG40) -40 to +85C industrial temperature operation 5P49V5907 MARCH 3, 2017 1 2017 Integrated Device Technology, Inc. SEL1/SD OUT0 SEL I2CB V 0 SEL0/SCL DDO OE buffer V DD V V DD DDO V OUT5 DDO NC OUT5B OEB 6,7 OEB 3,5 V 1 DDO V 4 DDO OUT1 OUT4 OUT1B OUT4B5P49V5907 DATASHEET Functional Block Diagram V 0 DDO XIN/REF OUT0 SEL I2CB XOUT V 1 DDO OUT1 SD/OE FOD1 OUT1B SEL1/SDA V 2 DDO OTP OUT2 SEL0/SCL and FOD2 Control Logic OUT2B PLL V DDA OEB V 3,5 DD CORE FOD3 V DDO OUT3, 5 OE buffer OEB 6,7 V DD OUT6, 7 V 4 DDO OUT4 FOD4 OUT4B Applications Ethernet switch/router PCI Express 1.0/2.0/3.0 Broadcast video/audio timing Multi-function printer Processor and FPGA clocking Any-frequency clock conversion MSAN/DSLAM/PON Fiber Channel, SAN Telecom line cards 1 GbE and 10 GbE PROGRAMMABLE CLOCK GENERATOR 2 MARCH 3, 2017