Programmable Clock Generator 5P49V5908 DATASHEET Description Features The 5P49V5908 is a programmable clock generator intended Generates up to four independent output frequencies with a for high performance consumer, networking, industrial, total of 11 differential outputs and one reference output computing, and data-communications applications. Supports multiple differential output I/O standards: Configurations may be stored in on-chip One-Time Three universal outputs pairs with each configurable 2 Programmable (OTP) memory or changed using I C as one differential output pair (LVDS, LVPECL or interface. This is IDTs fifth generation of programmable clock regular HCSL) or two LVCMOS outputs. Frequency technology (VersaClock 5). of each output pair can be individually programmed The frequencies are generated from a single reference clock Eight copies of Low Power HCSL(LP-HCSL) outputs. or crystal. Two select pins allow up to 4 different Programmable frequency configurations to be programmed and accessible using See Output Features and Descriptions for details processor GPIOs or bootstrapping. The different selections may be used for different operating modes (full function, One reference LVCMOS output clock partial function, partial power-down), regional standards (US, High performance, low phase noise PLL, < 0.7 ps RMS Japan, Europe) or system production margin testing. typical phase jitter on outputs: 2 The device may be configured to use one of two I C PCIe Gen1, 2, 3 compliant clock capability addresses to allow multiple devices to be used in a system. USB 3.0 compliant clock capability 1 GbE and 10 GbE Pin Assignment Four fractional output dividers (FODs) Independent Spread Spectrum capability from each fractional output divider (FOD) Four banks of internal non-volatile in-system programmable or factory programmable OTP memory 2 I C serial programming interface Input frequency ranges: 48 47 46 45 44 43 42 41 40 39 38 37 1 V 2 36 DDO LVCMOS Reference Clock Input (XIN/REF) 1MHz OUT10B OUT2 2 35 to 200MHz XOUT OUT2B 3 34 XIN/REF Crystal frequency range: 8MHz to 40MHz V 4 33 OEB DDA 7 10 Output frequency ranges: V 5 32 NC DDO LVCMOS Clock Outputs 1MHz to 200MHz 6 31 V OUT9 DD EPAD 7 V OUT9B 30 DD CORE LP-HCSL Clock Outputs 1MHz to 200MHz 29 OUT8 8 OUT3 Other Differential Clock Outputs 1MHz to 350MHz 28 9 OUT3B OUT8B Programmable loop bandwidth 10 27 V OUT7 DDO Programmable crystal load capacitance 11 26 NC OUT7B Power-down mode 12 25 NC SD/OE 14 15 16 17 18 19 20 21 22 23 24 13 Mixed voltage operation: 1.8V core 1.8V VDDO for 8 LP-HCSL outputs 1.8V to 3.3V VDDO for other outputs (3 programmable differential outputs and 1 reference 48-pin VFQFPN output) See Pin Descriptions for details Available in 48-pin VFQFPN package (NDG48) -40 to +85C industrial temperature operation 5P49V5908 MARCH 10, 2017 1 2017 Integrated Device Technology, Inc. SEL1/SD OUT10 SEL0/SCL OUT0 SEL I2CB V V 0 DD DDO V OE buffer DDO V OUT6 DD V DDO OUT6B OUT11B OUT5 OUT11 OUT5B NC V 4 DDO V 1 DDO OUT4 OUT1 OUT4B OUT1B OEB 3,115P49V5908 DATASHEET Functional Block Diagram V 0 DDO XIN/REF OUT0 SEL I2CB XOUT V 1 DDO OUT1 SD/OE FOD1 OUT1B SEL1/SDA V 2 DDO OTP OUT2 and SEL0/SCL FOD2 Control Logic OUT2B PLL V DDA OEB 3,11 V DDO OUT3, 5, 6, 11 FOD3 OE buffer OEB 7 10 V DD OUT7 - 10 V DD CORE V 4 DDO OUT4 FOD4 OUT4B Typical Applications Ethernet switch/router PCI Express 1.0/2.0/3.0 Broadcast video/audio timing Multi-function printer Processor and FPGA clocking Any-frequency clock conversion MSAN/DSLAM/PON Fiber Channel, SAN Telecom line cards 1 GbE and 10 GbE PROGRAMMABLE CLOCK GENERATOR 2 MARCH 10, 2017