Programmable Clock Generator 5P49V5927 DATASHEET Description Features The 5P49V5927 is a programmable clock generator intended Generates up to three independent output frequencies for high performance consumer, networking, industrial, High performance, low phase noise PLL, <0.7 ps RMS computing, and data-communications applications. typical phase jitter on outputs Configurations may be stored in on-chip One-Time 2 Three fractional output dividers (FODs) Programmable (OTP) memory or changed using I C interface. This is IDTs fifth generation of programmable clock Independent Spread Spectrum capability on each output technology (VersaClock 5). pair Four banks of internal non-volatile in-system The frequencies are generated from a single reference clock. programmable or factory programmable OTP memory The reference clock can come from one of the two redundant 2 clock inputs. A glitchless manual switchover function allows I C serial programming interface one of the redundant clocks to be selected during normal Seven LVCMOS outputs, including one reference output operation. I/O Standards: Two select pins allow up to 4 different configurations to be Single-ended I/Os: 1.8V to 3.3V LVCMOS programmed and accessible using processor GPIOs or bootstrapping. The different selections may be used for Input frequency ranges: different operating modes (full function, partial function, partial LVCMOS Reference Clock Input (XIN/REF) 1MHz to power-down), regional standards (US, Japan, Europe) or 200MHz system production margin testing. LVDS, LVPECL, HCSL Differential Clock Input (CLKIN, 2 The device may be configured to use one of two I C CLKINB) 1MHz to 200MHz addresses to allow multiple devices to be used in a system. Crystal frequency range: 8MHz to 40MHz Output frequency ranges: Pin Assignment LVCMOS Clock Outputs 1MHz to 200MHz Individually selectable output voltage (1.8V, 2.5V, 3.3V) for each output pair Redundant clock inputs with manual switchover Programmable loop bandwidth Programmable slew rate control Programmable crystal load capacitance Individual output enable/disable 24 23 22 21 20 19 1 V 2 18 DDO CLKIN Power-down mode 2 17 OUT3 CLKINB 1.8V, 2.5V or 3.3V core V , V DDD DDA XOUT 3 16 OUT4 EPAD Available in 24-pin VFQFPN 4mm x 4mm package GND 4 XIN/REF 15 V 3 DDO -40 to +85C industrial temperature operation 5 14 V OUT5 DDA 6 13 OUT6 CLKSEL 8 9 10 11 12 7 24-pin VFQFPN 5P49V5927 FEBRUARY 21, 2019 1 2019 Integrated Device Technology, Inc. SD/OE OUT0 SEL I2CB V 0 SEL1/SDA DDO SEL0/SCL V DDD V V 1 DDA DDO OUT1 NC OUT2 NC5P49V5927 DATASHEET Functional Block Diagram V 0 DDO XIN/REF OUT0 SEL I2CB XOUT V 1 DDO OUT1 FOD1 OUT2 CLKIN V 2 DDO CLKINB OUT3 FOD2 OUT4 CLKSEL PLL V 3 DDO SD/OE OUT5 FOD3 OUT6 SEL1/SDA V DDA OTP SEL0/SCL and Control Logic V DDA V DDD Applications Ethernet switch/router PCI Express 1.0/2.0/3.0 Broadcast video/audio timing Multi-function printer Processor and FPGA clocking Any-frequency clock conversion MSAN/DSLAM/PON Fiber Channel, SAN Telecom line cards 1 GbE and 10 GbE PROGRAMMABLE CLOCK GENERATOR 2 FEBRUARY 21, 2019