Programmable Clock Generator 5P49V5933 DATASHEET Description Features The 5P49V5933 is a programmable clock generator intended Generates up to two independent output frequencies for high-performance consumer, networking, industrial, High-performance, low-phase noise PLL, < 0.7ps RMS computing, and data-communications applications. typical phase jitter on outputs: Configurations may be stored in on-chip One-Time 2 PCIe Gen13 compliant clock capability Programmable (OTP) memory or changed using I C USB 3.0 compliant clock capability interface. This is IDTs fifth generation of programmable clock technology (VersaClock 5). 1GbE and 10GbE 5P49V5933 by default uses an integrated 25MHz crystal as Two fractional output dividers (FODs) input reference. It also has a redundant external clock input. Independent spread spectrum capability on each output A glitchless manual switchover functions allows selection of pair either one as mentioned above as input reference during Two banks of internal non-volatile in-system programmable normal operation or factory programmable OTP memory Two select pins allow up to 4 different configurations to be 2 I C serial programming interface programmed and accessible using processor GPIOs or One reference LVCMOS output clock bootstrapping. The different selections may be used for different operating modes (full function, partial function, partial Two universal output pairs: power-down), regional standards (US, Japan, Europe) or Each configurable as one differential output pair or two system production margin testing. LVCMOS outputs 2 The device may be configured to use one of two I C I/O Standards: addresses to allow multiple devices to be used in a system. Single-ended I/Os: 1.8V to 3.3V LVCMOS Differential I/Os: LVPECL, LVDS and HCSL Pin Assignment Input frequency ranges: LVDS, LVPECL, HCSL differential clock input (CLKIN, CLKINB) 1MHz to 350MHz Output frequency ranges: LVCMOS clock outputs: 1MHz to 200MHz LVDS, LVPECL, HCSL differential clock outputs: 1MHz to 350MHz 24 23 22 21 20 19 Individually selectable output voltage (1.8V, 2.5V, 3.3V) for 1 18 V DDA CLKIN each output pair 2 17 NC CLKINB Redundant clock inputs with manual switchover NC NC 3 16 EPAD 4 V Programmable loop bandwidth NC 15 DDA 5 14 V NC DDA Programmable output to output skew 6 13 NC CLKSEL Programmable slew rate control 8 7 910 11 12 Individual output enable/disable Power-down mode 1.8V, 2.5V or 3.3V core V , V DDD DDA 4 x 4 mm 24-LGA package -40 to +85C industrial temperature operation 4 4 mm 24-LGA 5P49V5933 NOVEMBER 1, 2017 1 2017 Integrated Device Technology, Inc. SD/OE OUT0 SEL I2CB V 0 SEL1/SDA DDO SEL0/SCL V DDD V 2 V 1 DDO DDO OUT1 OUT2 OUT1B OUT2B5P49V5933 DATASHEET Functional Block Diagram V 0 DDO OSC OUT0 SEL I2CB 25MHz V 1 DDO OUT1 CLKIN FOD1 OUT1B CLKINB PLL V 2 DDO CLKSEL OUT2 FOD2 SD/OE OUT2B SEL1/SDA OTP and SEL0/SCL Control Logic V DDA V DDD Typical Applications Ethernet switch/router PCI Express 1.0/2.0/3.0 Broadcast video/audio timing Multi-function printer Processor and FPGA clocking Any-frequency clock conversion MSAN/DSLAM/PON Fiber Channel, SAN Telecom line cards 1GbE and 10GbE PROGRAMMABLE CLOCK GENERATOR 2 NOVEMBER 1, 2017