Programmable Clock Generator 5P49V5943 DATASHEET Description Features The 5P49V5943 is a programmable clock generator intended Generates up to two independent output frequencies for high performance consumer, networking, industrial, High performance, low phase noise PLL, <0.7 ps RMS computing, and data-communications applications. typical phase jitter on outputs: Configurations may be stored in on-chip One-Time 2 PCIe Gen1, 2, 3 compliant clock capability Programmable (OTP) memory or changed using I C USB 3.0 compliant clock capability interface. This is IDTs fifth generation of programmable clock technology (VersaClock 5). 1 GbE and 10 GbE The frequencies are generated from a single input reference Two fractional output dividers (FODs) clock. Independent Spread Spectrum capability on each output pair Two select pins allow up to 4 different configurations to be programmed and accessible using processor GPIOs or Four banks of internal non-volatile in-system bootstrapping. The different selections may be used for programmable or factory programmable OTP memory different operating modes (full function, partial function, partial 2 I C serial programming interface power-down), regional standards (US, Japan, Europe) or One reference LVCMOS output clock system production margin testing. 2 Two universal output pairs: The device may be configured to use one of two I C addresses to allow multiple devices to be used in a system. Each configurable as one differential output pair or two LVCMOS outputs Pin Assignment I/O Standards: Single-ended I/Os: 1.8V to 3.3V LVCMOS Differential I/Os - LVPECL, LVDS and HCSL Input frequency ranges: LVDS, LVPECL, HCSL Differential Clock Input (CLKIN, CLKINB) 1MHz to 350MHz Output frequency ranges: LVCMOS Clock Outputs 1MHz to 200MHz LVDS, LVPECL, HCSL Differential Clock Outputs 20 19 18 17 16 1MHz to 350MHz 1 V 1 15 DDO CLKIN Individually selectable output voltage (1.8V, 2.5V, 3.3V) for 2 OUT1 14 CLKINB each output pair EPAD OUT1B 3 13 V DDA Programmable loop bandwidth 4 GND V 12 DD Programmable output to output skew 5 11 SD/OE GND Programmable slew rate control 6 7 8 910 Individual output enable/disable Power-down mode 1.8V, 2.5V or 3.3V core V , V DDD DDA Available in 20-pin VFQFPN 3mm x 3mm package -40 to +85C industrial temperature operation 20-pin VFQFPN 5P49V5943 MARCH 3, 2017 1 2017 Integrated Device Technology, Inc. OUT0 SEL I2CB SEL1/SDA V 0 SEL0/SCL DDO V 2 GND DDO V OUT2 DDD GND OUT2B5P49V5943 DATASHEET Functional Block Diagram V 0 DDO CLKIN OUT0 SEL I2CB CLKINB V 1 DDO SD/OE OUT1 PLL SEL1/SDA FOD1 OUT1B OTP SEL0/SCL and Control Logic V 2 DDO V DDA OUT2 V DDD FOD2 OUT2B Applications Ethernet switch/router PCI Express 1.0/2.0/3.0 Broadcast video/audio timing Multi-function printer Processor and FPGA clocking Any-frequency clock conversion MSAN/DSLAM/PON Fiber Channel, SAN Telecom line cards 1 GbE and 10 GbE PROGRAMMABLE CLOCK GENERATOR 2 MARCH 3, 2017