Programmable Clock Generator 5P49V5944 DATASHEET Description Features The 5P49V5944 is a programmable clock generator intended Generates up to two independent output frequencies for high-performance consumer, networking, industrial, High-performance, low phase noise PLL, < 0.7ps RMS computing, and data-communications applications. typical phase jitter on outputs: Configurations may be stored in on-chip One-Time 2 PCIe Gen13 compliant clock capability Programmable (OTP) memory or changed using I C USB 3.0 compliant clock capability interface. This is IDTs fifth generation of programmable clock technology (VersaClock 5). 1 GbE and 10 GbE The frequencies are generated from a single reference clock. Two fractional output dividers (FODs) The input reference can be either a crystal or an LVCMOS Independent spread spectrum capability on each output reference clock. pair Two select pins allow up to 4 different configurations to be Four banks of internal non-volatile in-system programmed and accessible using processor GPIOs or programmable or factory programmable OTP memory bootstrapping. The different selections may be used for 2 I C serial programming interface different operating modes (full function, partial function, partial One reference LVCMOS output clock power-down), regional standards (US, Japan, Europe) or system production margin testing. Two universal output pairs: 2 The device may be configured to use one of two I C Each configurable as one differential output pair or two addresses to allow multiple devices to be used in a system. LVCMOS outputs I/O standards: Pin Assignment Single-ended I/Os: 1.8V to 3.3V LVCMOS Differential I/Os: LVPECL, LVDS and HCSL Input frequency ranges: LVCMOS reference clock input (XIN/REF): 1MHz to 200MHz Crystal frequency range: 8MHz to 40MHz Output frequency ranges: LVCMOS clock outputs: 1MHz to 200MHz 20 19 18 17 16 LVDS, LVPECL, HCSL differential clock outputs: 1MHz 1 15 V 1 XOUT DDO to 350MHz 2 14 OUT1 XIN/REF Individually selectable output voltage (1.8V, 2.5V, 3.3V) for 3 EPAD 13 V OUT1B each output pair DDA 4 GND 12 GND Programmable loop bandwidth 5 11 GND SD/OE Programmable output to output skew 7 8 6 910 Programmable slew rate control Programmable crystal load capacitance Individual output enable/disable Power-down mode 1.8V, 2.5V or 3.3V core V , V DDD DDA 3 x 3 mm 20-VFQFPN package 3 3 mm 20-VFQFPN -40 to +85C industrial temperature operation 5P49V5944 JULY 10, 2019 1 OUT0 SEL I2CB SEL1/SDA SEL0/SCL V 0 DDO V 2 GND DDO V OUT2 DDD GND OUT2B5P49V5944 DATASHEET Functional Block Diagram V 0 DDO OUT0 SEL I2CB XIN/REF XOUT V 1 DDO SD/OE OUT1 PLL FOD1 SEL1/SDA OUT1B OTP SEL0/SCL and Control Logic V 2 DDO V DDA OUT2 V DDD FOD2 OUT2B Applications Ethernet switch/router PCI Express 1.0/2.0/3.0 Broadcast video/audio timing Multi-function printer Processor and FPGA clocking Any-frequency clock conversion MSAN/DSLAM/PON Fiber channel, SAN Telecom line cards 1 GbE and 10 GbE PROGRAMMABLE CLOCK GENERATOR 2 JULY 10, 2019