VersaClock 6E Programmable 5P49V6965 Clock Generator Datasheet Description Features Flexible 1.8V, 2.5V, 3.3V power-rails The 5P49V6965 is a programmable clock generator intended for high-performance consumer, networking, industrial, computing, High-performance, low phase noise PLL, < 0.5ps RMS typical and data-communications applications. Configurations may be phase jitter on outputs stored in on-chip One-Time Programmable (OTP) memory or Four banks of internal OTP memory 2 changed using I C interface. This is Renesas sixth generation of In-system or factory programmable programmable clock technology (VersaClock 6E). 2 select pins accessible with processor GPIOs or The frequencies are generated from a single reference clock. The bootstrapping reference clock can come from one of the two redundant clock 2 I C serial programming interface inputs. A glitchless manual switchover function allows one of the 0xD0 or 0xD4 I2C address options allows multiple devices redundant clocks to be selected during normal operation. configured in a same system Two select pins allow up to four different configurations to be Reference LVCMOS output clock programmed and accessible using processor GPIOs or Four universal output pairs individually configurable: bootstrapping. The different selections may be used for different Differential (LVPECL, LVDS or HCSL) operating modes (full function, partial function, partial power-down), regional standards (US, Japan, Europe) or system 2 single-ended (2 LVCMOS in-phase or 180 degrees out of production margin testing. The device may be configured to use phase) 2 one of two I C addresses to allow multiple devices to be used in a I/O V s can be mixed and matched, supporting 1.8V DD system. (LVDS and LVCMOS), 2.5V, or 3.3V Output frequency ranges: Typical Applications LVCMOS clock outputs: 1kHz to 200MHz Ethernet switch/router LVDS, LVPECL, HCSL differential clock outputs: 1kHz to PCI Express 1.0 / 2.0 / 3.0 / 4.0 Spread Spectrum on 350MHz PCI Express 1.0 / 2.0 / 3.0 / 4.0 / 5.0 Spread Spectrum off Redundant clock inputs with manual switchover Broadcast video/audio timing Programmable output enable or power-down mode Multi-function printer Available in 4 4 mm 24-VFQFPN package Processor and FPGA clocking -40 to +85C industrial temperature operation Any-frequency clock conversion MSAN/DSLAM/PON Fiber Channel, SAN Telecom line cards Laser distance sensing Block Diagram V 0 DDO XIN/REF OUT0 SEL I2CB VDDO1 XOUT OUT1 CLKIN FOD1 OUT1B CLKINB V 2 DDO CLKSEL OUT2 FOD2 SD/OE OTP OUT2B PLL and SEL1/SDA VDDO3 Control SEL0/SCL Logic OUT3 VDDA FOD3 V OUT3B DDD VDDO4 OUT4 FOD4 OUT4B 2021 Renesas Electronics Corporation 1 R31DS0062EU0601 July 6, 20215P49V6965 Datasheet Contents Description 1 Typical Applications . 1 Features 1 Block Diagram . 1 Pin Assignments 3 Pin Descriptions 3 Absolute Maximum Ratings . 5 Thermal Characteristics 5 Recommended Operating Conditions . 5 Electrical Characteristics . 6 I2C Bus Characteristics . 11 Test Loads . 12 Jitter Performance Characteristics . 13 PCI Express Jitter Performance and Specification 14 Features and Functional Blocks . 16 Device Startup and Power-On-Reset 16 Reference Clock and Selection . 16 Manual Switchover 16 Internal Crystal Oscillator (XIN/REF) 17 Programmable Loop Filter . 18 Fractional Output Dividers (FOD) . 18 Output Drivers 18 SD/OE Pin Function . 19 I2C Operation 19 Typical Application Circuits 20 Input Driving the XIN/REF or CLKIN . 21 Output Single-ended or Differential Clock Terminations 23 Package Outline Drawings . 26 Marking Diagram 26 Ordering Information . 26 Revision History . 27 2021 Renesas Electronics Corporation 2 R31DS0062EU0601 July 6, 2021