VersaClock 6E Programmable 5P49V6975 Clock with Internal Crystal Datasheet Description Features The 5P49V6975 is a programmable clock generator intended for Internal crystal input integrated into package high-performance consumer, networking, industrial, computing, Flexible 1.8V, 2.5V, 3.3V power rails and data-communications applications. The device is a member of High-performance, low phase noise PLL, < 0.5ps RMS typical Renesas sixth generation of programmable clock technology, phase jitter on outputs VersaClock 6E. Four banks of internal OTP memory The 5P49V6975 contains an internal crystal, which eliminates the In-system or factory programmable need for external crystal and load cap tuning. Two select pins accessible with processor GPIOs or Two select pins allow up to four different configurations to be bootstrapping programmed, and can be used for different operating modes (full 2 I C serial programming interface function, partial function, partial power-down), regional standards 2 0xD0 or 0xD4 I C address options allow multiple devices (US, Japan, Europe) or system production margin testing. The 2 configured in a same system 5P49V6975 can be configured to use one of two I C addresses to allow the use of multiple devices in a system. Reference LVCMOS output clock Four universal output pairs individually configurable: Typical Applications Differential (LVPECL, LVDS, or HCSL) Ethernet switch/router Two single-ended (2 LVCMOS in-phase or 180 degrees out of phase) PCI Express 1.0/2.0/3.0/4.0 spread spectrum on I/O VDDs can be mixed and matched, supporting 1.8V PCI Express 1.0/2.0/3.0/4.0/5.0 spread spectrum off (LVDS and LVCMOS), 2.5V, or 3.3V Broadcast video/audio timing Independent spread spectrum on each output pair Multi-function printer Output frequency ranges: Processor and FPGA clocking LVCMOS clock outputs: 1kHz to 200MHz Any-frequency clock conversion LVDS, LVPECL, HCSL differential clock outputs: 1kHz to MSAN/DSLAM/PON 350MHz Fiber Channel, SAN Programmable output enable or power-down mode Telecom line cards Available in 4 4 mm 24-LGA package Laser distance sensing -40 to +85C industrial temperature operation Block Diagram V 0 DDO OUT0 SEL I2CB VDDO1 OUT1 CLKIN FOD1 OUT1B CLKINB VDDO2 CLKSEL OUT2 FOD2 SD/OE OTP OUT2B PLL and SEL1/SDA Control VDDO3 SEL0/SCL Logic OUT3 V DDA FOD3 VDDD OUT3B V 4 DDO OUT4 FOD4 OUT4B 2021 Renesas Electronics Corporation. 1 February 11, 2021 5P49V6975 Datasheet Contents 1. Pin Assignments ...........................................................................................................................................................................................3 2. Pin Descriptions ............................................................................................................................................................................................3 3. Absolute Maximum Ratings ..........................................................................................................................................................................5 4. Thermal Characteristics ................................................................................................................................................................................5 5. Recommended Operating Conditions...........................................................................................................................................................5 6. Electrical Characteristics ..............................................................................................................................................................................6 7. Test Loads ..................................................................................................................................................................................................13 8. Jitter Performance Characteristics..............................................................................................................................................................14 9. PCI Express Jitter Performance and Specification .....................................................................................................................................15 10. Features and Functional Blocks .................................................................................................................................................................17 10.1 Device Startup and Power-on-Reset ................................................................................................................................................17 10.2 Reference Clock and Selection ........................................................................................................................................................18 10.3 Manual Switchover ...........................................................................................................................................................................18 10.4 Programmable Loop Filter................................................................................................................................................................19 10.5 Fractional Output Dividers (FOD) .....................................................................................................................................................19 10.5.1 Individual Spread Spectrum Modulation ...........................................................................................................................19 10.5.2 Bypass Mode ....................................................................................................................................................................19 10.5.3 Cascaded Mode ................................................................................................................................................................19 10.5.4 Dividers Alignment ............................................................................................................................................................19 10.5.5 Programmable Skew .........................................................................................................................................................20 10.6 Output Drivers ..................................................................................................................................................................................20 10.7 SD/OE Pin Function .........................................................................................................................................................................20 2 10.8 I C Operation ...................................................................................................................................................................................21 11. Typical Application Circuit ..........................................................................................................................................................................22 11.1 Input Driving the CLKIN ................................................................................................................................................................23 11.1.1 Wiring the CLKIN Pin to Accept Single-Ended Inputs .......................................................................................................23 11.1.2 Driving CLKIN with Differential Clock ................................................................................................................................24 11.2 Output Single-ended or Differential Clock Terminations ...............................................................................................................24 11.2.1 LVDS Termination .............................................................................................................................................................24 11.2.2 LVPECL Termination ........................................................................................................................................................25 11.2.3 HCSL Termination.............................................................................................................................................................26 11.2.4 LVCMOS Termination .......................................................................................................................................................26 12. Package Outline Drawings .........................................................................................................................................................................26 13. Marking Diagram .........................................................................................................................................................................................27 14. Ordering Information ...................................................................................................................................................................................27 15. Revision History ..........................................................................................................................................................................................28 2021 Renesas Electronics Corporation. 2 February 11, 2021