5V19EE404NLGI Renesas

DATASHEET EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR IDT5V19EE404 Description Features The IDT5V19EE404 is a programmable clock generator Four internal PLLs intended for high performance data-communications, Internal non-volatile EEPROM telecommunications, consumer, and networking 2 Fast (400kHz) mode I C serial interface applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related Input frequency range: 1 MHz to 200 MHz frequencies. The frequencies are generated from a single Output frequency range: 4.9 kHz to 200 MHz reference clock. The reference clock can come from one of Reference crystal input with programmable linear load the two redundant clock inputs. Automatic or manual capacitance switchover function allows any one of the redundant clocks to be selected during normal operation. Crystal frequency range: 8 MHz to 50 MHz The IDT5V19EE404 is in-system, programmable and can Integrated VCXO 2 be programmed through the use of I C interface. An Two independently controlled VDDO (1.8V - 3.3V) internal EEPROM allows the user to save and restore the Each PLL has a 7-bit reference divider and a 12-bit configuration of the device without having to reprogram it on feedback-divider power-up. 8-bit output-divider blocks Each of the four PLLs has an 7-bit reference divider and a Fractional division capability on one PLL 12-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop Two of the PLLs support spread spectrum generation bandwidth is programmable to allow the user to tailor the capability PLL response to the application. For instance, the user can I/O Standards: tune the PLL parameters to minimize jitter generation or to Outputs - 1.8 - 3.3 V LVTTL/ LVCMOS maximize jitter attenuation. Spread spectrum generation and/or fractional divides are allowed on two of the PLLs. Inputs - 3.3 V LVTTL/ LVCMOS There are a total of four 8-bit output dividers.The outputs Programmable slew rate control are connected to the PLLs via a switch matrix. The switch Programmable loop bandwidth matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and Programmable output inversion to reduce bimodal jitter optimize the board layout. In addition, each output s slew Redundant clock inputs with auto and manual switchover rate and enable/disable function is programmable. options Individual output enable/disable Power-down mode 3.3V core V DD Available in VFQFPN package -40 to +85C Industrial Temp operation IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR 1 IDT5V19EE404 REV M 092412IDT5V19EE404 EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR CLOCK SYNTHESIZER Functional Block Diagram XIN/REF XOUT S S1 PLL0 (SS) R /DIV1 C OUT1 VCXO 1 VIN controlled Logic S CLKIN R PLL1 /DIV2 OUT2 C 2 CLKSEL PLL2 S S3 R /DIV3 C PLL3 (SS) OUT3 3 S R SD/OE /DIV6 OUT6 C 6 SDA Control Logic SCL SEL 2:0 1. CLKIN, CLKSEL, SD/OE and SEL 2:0 have pull down resistors. IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR 2 IDT5V19EE404 REV M 092412