5V41067APGGI Renesas

DATASHEET 2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER IDT5V41067A Description Features/Benefits The IDT5V41067A is a 2:4 differential clock mux for PCI Low additive jitter suitable for use in PCIe Gen2 and Express applications. It has very low additive jitter making it Gen3 systems suitable for use in PCIe Gen2 and Gen3 systems. The 20-pin TSSOP package small board footprint IDT5V41067A selects between 1 of 2 differential HCSL Outputs can be terminated to LVDS can drive a wider inputs to fanout to 4 differential HCSL output pairs. The variety of devices outputs can also be terminated to LVDS. OE control pin greater system power management Recommended Applications Industrial temperature range available supports demanding embedded applications Clock muxing in PCIe Gen2 and Gen3 applications Key Specifications Output Features Additive cycle-to-cycle jitter <5 ps 4 0.7V current mode differential HCSL output pairs Additive phase jitter (PCIe Gen2/3) <0.2ps Operating frequency up to 200MHz Block Diagram OE VDD 2 CLKA CLKA IN1 CLKB IN1 CLKB MUX 2 to 1 IN2 CLKC CLKC IN2 CLKD CLKD 2 Rr (IREF) SEL GND PD IDT 2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER 1 IDT5V41067A REV F 112211IDT5V41067A 2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER Pin Assignment Select Table SEL 1 20 DIF 0 SEL Outputs VDDIN 2 19 DIF 0 DIF IN1 3 18 DIF 1 0DIF IN2 DIF IN1 4 17 DIF 1 1DIF IN1 PD 5 16 GND DIF IN2 6 15 VDD DIF IN2 7 14 DIF 2 OE 8 13 DIF 2 GND 9 12 DIF 3 10 11 DIF 3 IREF Note: Pins preceeded by * have internal 120K ohm pull up resistors 20-pin (173mil) TSSOP Pin Descriptions PIN PIN NAME PIN TYPE DESCRIPTION 1 SEL IN Selects between one of two inputs. This pin has internal pull up resistor. 2 VDDIN PWR Power pin for the Inputs, nominal 3.3V 3 DIF IN1 IN 0.7 V Differential TRUE input 4 DIF IN1 IN 0.7 V Differential Complementary Input Asynchronous active low input pin used to power down the device. The internal 5 PD IN c locks are dis abled and the VCO and the crystal os c. (if any) are stopped. 6 DIF IN2 IN 0.7 V Differential TRUE input 7 DIF IN2 IN 0.7 V Differential Complementary Input Active high input for enabling outputs. This pin has an internal pull up resistor. 8 OE IN 0 = disable outputs, 1= enable outputs 9 GND PWR Ground pin. This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is the standard value for 10 IREF OUT 100ohm differential impedance. Other impedances require different values. See data sheet. 11 DIF 3 OUT 0.7V differential Complementary clock output 12 DIF 3 OUT 0.7V differential true clock output 13 DIF 2 OUT 0.7V differential Complementary clock output 14 DIF 2 OUT 0.7V differential true clock output 15 VDD PWR Power supply, nominal 3.3V 16 GND PWR Ground pin. 17 DIF 1 OUT 0.7V differential Complementary clock output 18 DIF 1 OUT 0.7V differential true clock output 19 DIF 0 OUT 0.7V differential Complementary clock output 20 DIF 0 OUT 0.7V differential true clock output IDT 2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER 2 IDT5V41067A REV F 112211 5V41067