5V41068APGGI8 Renesas

DATASHEET 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER IDT5V41068A Description Features/Benefits The IDT5V41068A is a 2:1 differential clock mux for PCI Low additive jitter suitable for use in PCIe Gen2 and Express applications. It has very low additive jitter making it Gen3 systems suitable for use in PCIe Gen2 and Gen3 systems. The 16-pin TSSOP package small board footprint IDT5V41068A selects between 1 of 2 differential HCSL Outputs can be terminated to LVDS can drive a wider inputs to drive a single differential HCSL output pair. The variety of devices output can also be terminated to LVDS. OE control pin greater system power management Recommended Applications Industrial temperature range available supports demanding embedded applications Clock muxing in PCIe Gen2 and Gen3 applications Key Specifications Output Features Additive cycle-to-cycle jitter <5 ps 1 0.7V current mode differential HCSL output pair Additive phase jitter (PCIe Gen3) <0.2ps Operating frequency up to 200MHz Block Diagram OE VDD 3 IN1 CLK IN1 MUX 2 to 1 IN2 CLK IN2 3 Rr (IREF) SEL GND PD IDT 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 1 IDT5V41068A REV F 040616IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Pin Assignment Select Table VDDIN 1 16 SEL SEL Outputs DIF IN1 2 15 DIF 0 DIF IN1 3 14 DIF 0 0DIF IN2 PD 4 13 GND 1DIF IN1 DIF IN2 5 12 GND DIF IN2 6 11 VDD OE 7 10 VDD 89 GND IREF Note: Pins preceeded by * have internal 120K ohm pull up resistors 16-pin TSSOP Pin Descriptions PIN PIN NAME PIN TYPE DESCRIPTION 1 VDDIN PWR Power pin for the Inputs, nominal 3.3V 2 DIF IN1 IN 0.7 V Differential TRUE input 3 DIF IN1 IN 0.7 V Differential Complementary Input Asynchronous active low input pin used to power down the device. The internal 4 PD IN c locks are dis abled and the VCO and the crystal os c. (if any) are stopped. 5 DIF IN2 IN 0.7 V Differential TRUE input 6 DIF IN2 IN 0.7 V Differential Complementary Input Active high input for enabling outputs. This pin has an internal pull up resistor. 7 OE IN 0 = disable outputs, 1= enable outputs 8 GND PWR Ground pin. This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is the standard value for 9IREF OUT 100ohm differential impedance. Other impedances require different values. See data sheet. 10 VDD PWR Power supply, nominal 3.3V 11 VDD PWR Power supply, nominal 3.3V 12 GND PWR Ground pin. 13 GND PWR Ground pin. 14 DIF 0 OUT 0.7V differential Complementary clock output 15 DIF 0 OUT 0.7V differential true clock output 16 SEL IN Selects between one of two inputs. This pin has internal pull up resistor. IDT 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 2 IDT5V41068A REV F 040616 5V41068