5V41235PGG8 Renesas

DATASHEET 2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 5V41235 Recommended Applications Features/Benefits 2 Output synthesizer for PCIe Gen1/2/3 and Ethernet 16-pin TSSOP and QFN packages small board footprint Spread-spectrum capable reduces EMI General Description Outputs can be terminated to LVDS can drive a wider variety of devices The 5V41235 is a PCIe Gen2/3 compliant spread spectrum TSSOP package: 25MHz, 100MHz, 125MHz and capable clock generator. The device has 2 differential 200MHz output frequencies. HCSL outputs and can be used in communication or embedded systems to substantially reduce QFN package: 100MHz and 200MHz output frequencies. electro-magnetic interference (EMI). The spread amount OE control pin greater system power management and output frequency are selectable via select pins. The Spread% and frequency pin selection no software 5V41235 can also supply 25 MHz, 125 MHz and 200 MHz required to configure device outputs for applications such as Ethernet. Industrial temperature range available supports demanding embedded applications Output Features 2 - 0.7V current mode differential HCSL output pairs Key Specifications Cycle-to-cycle jitter < 100 ps Output-to-output skew < 50 ps PCIe Gen2 phase jitter < 3.0ps RMS PCIe Gen3 phase jitter <1.0ps RMS Block Diagram VDD 2 SS1:SS0 CLK0 2 Control CLK0 Logic S1:S0 2 Phase Lock Loop CLK1 X1/ICLK Clock CLK1 Buffer/ 25 MHz Crystal crystal or clock Oscillator X2 2 Optional tuning crystal Rr(IREF) capacitors GND OE IDT 2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 1 5V41235 MAY 5, 20175V41235 2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Pin Assignments 1 16 VDDXD S0 S1 2 15 CLK0 16 15 14 13 SS0 3 14 CLK0 S1 1 12 GNDODA X1/ICLK 4 13 GNDODA SS0 2 11 VDDODA 5V41235 X2 5 12 VDDODA X1/CLK 3 10 CLK1 OE 6 11 CLK1 X2 4 9 CLK1 56 78 7 10 GNDXD CLK1 8 9 SS1 IREF 16-pin (173 mil) TSSOP 16-pin QFN Output Select Table 1 (MHz) - TSSOP Only Output/Spread Select Table 3 - QFN Only S1 S0 SS1 SS0 Output Spread% S1 S0 CLK(1:0), CLK(1:0) 00 00 100MHz -0.5 00 25M 00 01 200MHz -0.5 0 1 100M 0 0 1 0 100MHz No spread 1 0 125M 00 11 Reserved 1 1 200M 01 00 100MHz -1 01 01 200MHz -1 Spread Selection Table 2 - TSSOP Only 01 10 Reserved SS1 SS0 Spread% 01 11 Reserved 00 No Spread 10 00 100MHz -1.5 0 1 Down -0.5 10 01 200MHz -1.5 1 0 Down -0.75 10 10 Reserved 11 No Spread 10 11 Reserved 11 00 Reserved 1 1 0 1 200MHz No spread 11 10 Reserved 11 11 Reserved IDT 2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 2 5V41235 MAY 5, 2017 OE S0 GNDXD VDDXD SS1 CLK0 IREF CLK0