DATASHEET EEPROM PROGRAMMABLE CLOCK GENERATOR IDT5V49EE701 Description Features The IDT5V49EE701 is a programmable clock generator Four internal PLLs intended for high performance data-communications, Internal non-volatile EEPROM telecommunications, consumer, and networking 2 Fast (400kHz) mode I C serial interface applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related Input frequency range: 1 MHz to 200 MHz frequencies. The frequencies are generated from a single Output frequency range: 4.9 kHz to 500 MHz reference clock. The reference clock can come from one of Reference crystal input with programmable linear load the two redundant clock inputs. Automatic or manual capacitance switchover function allows any one of the redundant clocks to be selected during normal operation. Crystal frequency range: 8 MHz to 50 MHz The IDT5V49EE701 is in-system, programmable and can Each PLL has a 7-bit reference divider and a 12-bit 2 be programmed through the use of I C interface. An feedback-divider internal EEPROM allows the user to save and restore the 8-bit output-divider blocks configuration of the device without having to reprogram it on Fractional division capability on one PLL power-up. Two of the PLLs support spread spectrum generation Each of the four PLLs has an 7-bit reference divider and a capability 12-bit feedback divider. This allows the user to generate I/O Standards: four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the Outputs - 3.3 V LVTTL/ LVCMOS PLL response to the application. For instance, the user can Outputs - LVPECL, LVDS and HCSL tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation Inputs - 3.3 V LVTTL/ LVCMOS and/or fractional divides are allowed on two of the PLLs. Programmable slew rate control There are a total of five 8-bit output dividers. Each output Programmable loop bandwidth bank can be configured to support LVTTL, LVPECL, LVDS Programmable output inversion to reduce bimodal jitter or HCSL logic levels. Out0 (Output 0) supports 3.3V single-ended output only. The outputs are connected to the Redundant clock inputs with auto and manual switchover PLLs via a switch matrix. The switch matrix allows the user options to route the PLL outputs to any output bank. This feature Individual output enable/disable can be used to simplify and optimize the board layout. In Power-down mode addition, each output s slew rate and enable/disable function is programmable. 3.3V core V DD Available in VFQFPN package -40 to +85 C Industrial Temp operation IDT EEPROM PROGRAMMABLE CLOCK GENERATOR 1 IDT5V49EE701 REV P 071015IDT5V49EE701 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCKSYNTHESIZER Functional Block Diagram S R OUT0 C XIN/REF 0 XOUT S S1 PLL0 (SS) R /DIV1 C OUT1 1 S CLKIN R PLL1 /DIV2 OUT2 C 2 CLKSEL PLL2 S S3 R /DIV3 C PLL3 (SS) OUT3 3 S R SD/OE /DIV6 OUT6 C 6 SDA Control S OUT5 Logic SCL R /DIV5 C OUT5 5 SEL 2:0 1. OUT1 & OUT2, OUT3 & OUT6, and OUT5 & OUT5 pairs can be configured to be LVDS, LVPECL or HCSL, or two single-ended LVTTL outputs. 2. CLKIN, CLKSEL, SD/OE and SEL 2:0 have pull down resistors. IDT EEPROM PROGRAMMABLE CLOCK GENERATOR 2 IDT5V49EE701 REV P 071015