5V49EE703NDGI Renesas

DATASHEET EEPROM PROGRAMMABLE CLOCK GENERATOR IDT5V49EE703 Description Features The IDT5V49EE703 is a programmable clock generator Four internal PLLs intended for high performance data-communications, Internal non-volatile EEPROM telecommunications, consumer, and networking 2 Fast (400kHz) mode I C serial interface applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related Input frequency range: 1 MHz to 200 MHz frequencies. The frequencies are generated from a single Output frequency range: 4.9 kHz to 200 MHz reference clock. The reference clock can come from one of Reference crystal input with programmable linear load the two redundant clock inputs. Automatic or manual capacitance switchover function allows any one of the redundant clocks to be selected during normal operation. Crystal frequency range: 8 MHz to 50 MHz The IDT5V49EE703 is in-system, programmable and can Each PLL has a 7-bit reference divider and a 12-bit 2 be programmed through the use of I C interface. An feedback-divider internal EEPROM allows the user to save and restore the 8-bit output-divider blocks configuration of the device without having to reprogram it on Fractional division capability on one PLL power-up. Two of the PLLs support spread spectrum generation Each of the four PLLs has an 7-bit reference divider and a capability 12-bit feedback divider. This allows the user to generate I/O Standards: four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the Outputs - 3.3 V LVTTL/ LVCMOS PLL response to the application. For instance, the user can Inputs - 3.3 V LVTTL/ LVCMOS tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation Programmable slew rate control and/or fractional divides are allowed on two of the PLLs. Programmable loop bandwidth There are a total of five 8-bit output dividers. The outputs Programmable output inversion to reduce bimodal jitter are connected to the PLLs via a switch matrix. The switch Redundant clock inputs with auto and manual switchover matrix allows the user to route the PLL outputs to any options output bank. This feature can be used to simplify and optimize the board layout. In addition, each output s slew Individual output enable/disable rate and enable/disable function is programmable. Power-down mode 3.3V core V DD Available in TSSOP and VFQFPN packages -40 to +85 C Industrial Temp operation IDT EEPROM PROGRAMMABLE CLOCK GENERATOR 1 IDT5V49EE703 REV N 071015IDT5V49EE703 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCKSYNTHESIZER Functional Block Diagram S R OUT0 C XIN/REF 0 XOUT S S1 PLL0 (SS) R /DIV1 C OUT1 1 S CLKIN R PLL1 /DIV2 OUT2 C 2 CLKSEL PLL2 S S3 R /DIV3 C PLL3 (SS) OUT3 3 S R SD/OE /DIV6 OUT6 C 6 SDA Control S OUT5 Logic SCL R /DIV5 C OUT5 5 SEL 2:0 1. CLKIN, CLKSEL, SD/OE and SEL 2:0 have pull down resistors. IDT EEPROM PROGRAMMABLE CLOCK GENERATOR 2 IDT5V49EE703 REV N 071015