5V80001PGGI8 Renesas

DATASHEET MOST CLOCK INTERFACE IDT5V80001 Description Features The IDT5V80001 is a high performance clock interface for Packaged in 20-pin TSSOP use in MOST (Media Oriented Systems Transport) -40 to +85C temperature range (industrial) enabled systems. It can be used in two modes: generating Compliant to AEC Q100 a master clock for the ring, or performing clock/data recovery in a slave node. Operating voltage of 3.3 V 5 volt tolerant input for FOT Low jitter generation Power-down tri-state mode Advanced, low-power CMOS process Block Diagram BYPASS FOT IN 1 FOT OUT Retiming 0 MOST Din MUX 0 1 RESET CDR PLL INPUT COPY RCLK X1 Crystal Master MCLK Oscillator PLL X2 S1 S0 OEM IDT MOST CLOCK INTERFACE 1 IDT5V80001 REV S 083109IDT5V80001 MOST CLOCK INTERFACE SYNTHESIZERS Pin Assignment Frequency Selection Tables S1 S0 Operating Mode Sampling X2 1 20 NC Frequency (RCLK) Frequency 2 X1 19 MOST Din 3 INPUT COPY 0 0 45.1584 MHz MOST 25 44.1 kHz RESET 18 VDD 4 17 VDD 0 1 49.152 MHz MOST 25 48 kHz 5 FOT OUT 16 RCLK 1 0 90.3168 MHz MOST 50 44.1 kHz GND 6 15 GND 7 1 1 98.304 MHz MOST 50 48 kHz S1 14 MCLK 8 13 OEM FOT IN 9 S0 BYPASS 12 LF 10 11 LFR OEM MCLK Output Source for Retiming Block 20-pin TSSOP 0 LOW RCLK (slave node) 1 Running MCLK (master node) OEM Node Bypass FOT OUT 0 Slave 0 Retimed (RCLK) MOST Din* 1FOT IN 1 Master 0 Retimed (MCLK) MOST Din 1FOT IN * FOT IN must be present in order to generate RCLK and Retimed (RCLK) MOST Din. Pin Descriptions Pin Name Type Pin Description 1 X2 Input Connect to 21.504 MHz crystal. 2 X1 Input Connect to 21.504 MHz crystal. 3 RESET Input Low to reset CDR PLL. Internal pull-up resistor. 4 VDD Power Connect to 3.3 V supply. 5 FOT OUT Output Output for fiber optic MOST transceiver. 3.3 V LVTTL levels. 6 GND Power Connect to ground. 7 S1 Input Frequency select input pin. See table above. No internal pull-up or pull-down resistor. 8 FOT IN Input Input to device from fiber optic MOST transceiver. 3.3 V LVTTL levels, 5 V tolerant. 9 S0 Input Frequency select input pin. See table above. No internal pull-up or pull-down resistor. IDT MOST CLOCK INTERFACE 2 IDT5V80001 REV S 083109