IDT5V9885T 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE 3.3V EEPROM IDT5V9885T PROGRAMMABLE CLOCK GENERATOR FEATURES: DESCRIPTION: Three internal PLLs The IDT5V9885T is a programmable clock generator intended for high Internal non-volatile EEPROM performance data-communications, telecommunications, consumer, and 2 JTAG and FAST mode I C serial interfaces networking applications. There are three internal PLLs, each individually Input Frequency Ranges: 1MHz to 400MHz programmable, allowing for three unique non-integer-related frequencies. Output Frequency Ranges: 4.9kHz to 500MHz The frequencies are generated from a single reference clock. The Reference Crystal Input with programmable oscillator gain and reference clock can come from one of the two redundant clock inputs. A programmable linear load capacitance glitchless automatic or manual switchover function allows any one of the Crystal Frequency Range: 8MHz to 50MHz redundant clocks to be selected during normal operation. 2 Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider The IDT5V9885T can be programmed through the use of the I C or 10-bit post-divider blocks JTAG interfaces. The programming interface enables the device to be Fractional Dividers programmed when it is in normal operation or what is commonly known as Two of the PLLs support Spread Spectrum Generation in-system programmable. An internal EEPROM allows the user to save capability and restore the configuration of the device without having to reprogram it I/O Standards: on power-up. JTAG boundary scan is also implemented. Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback Inputs - 3.3V LVTTL/ LVCMOS divider. This allows the user to generate three unique non-integer-related Programmable Slew Rate Control frequencies. The PLL loop bandwidth is programmable to allow the user Programmable Loop Bandwidth Settings to tailor the PLL response to the application. For instance, the user can tune Programmable output inversion to reduce bimodal jitter the PLL parameters to minimize jitter generation or to maximize jitter Redundant clock inputs with glitchless auto and manual attenuation. Spread spectrum generation and fractional divides are switchover options allowed on two of the PLLs. JTAG Boundary Scan There are 10-bit post dividers on five of the six output banks. Two of the Individual output enable/disable six output banks are configurable to be LVTTL, LVPECL, or LVDS. The Power-down mode other four output banks are LVTTL. The outputs are connected to the PLLs 3.3V VDD via the switch matrix. The switch matrix allows the user to route the PLL Available in TQFP and VFQFPN packages outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output s slew rate and enable/disable function can be programmed. INDUSTRIAL TEMPERATURE RANGE SEPT. 2011 1 c 2011 Integrated Device Technology, Inc. DSC 7117/4IDT5V9885T 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM XTALOUT OSC. XTALIN/REFIN OUT1 P2 Divider 10-Bit /2 OUT2 P3 Divider PLL 0 10-Bit /2 OUT3 CLKIN (1) OUT4 P4 Divider PLL 1 10-Bit /2 (1) OUT4 (1) OUT5 PLL 2 P5 Divider SHUTDOWN/OE 10-Bit /2 (1) OUT5 P6 Divider EEPROM 10-Bit /2 OUT6 GOUT0/TDO/ GIN5/CLK SEL LOSS LOCK Control Block for Multi-Purpose I/O, Programming, Features 2 GOUT1/ I C/JTAG LOSS CLKIN NOTE: 1. OUT4 and OUT5 pairs can be configured to be LVDS, LVPECL, or two single-ended LVTTL outputs. As LVTTL, OUT4 and OUT5 can be configured to be non-inverting. 2 GIN0/SDAT/TDI GIN2/TMS GIN1/SCLK/TCLK GIN3/SUSPEND GIN4/TRST