3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER
IDT5V995
TURBOCLOCK II
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCTOBER 28, 2014
FEATURES: DESCRIPTION:
Ref input is 5V tolerant The IDT5V995 is a high fanout 3.3V PLL based clock driver
4 pairs of programmable skew outputs intended for high performance computing and data-communica-
Low skew: 185ps same pair, 250ps all outputs tions applications. A key feature of the programmable skew is the
Selectable positive or negative edge synchroniza- ability of outputs to lead or lag the REF input signal. The
tion: IDT5V995 has eight programmable skew outputs in four banks of
Excellent for DSP applications 2. Skew is controlled by 3-level input signals that may be hard-
Synchronous output enable wired to appropriate HIGH-MID-LOW levels.
Input frequency: 2MHz to 200MHz The feedback input allows divide-by-functionality from 1 to 12
Output frequency: 6MHz to 200MHz through the use of the DS[1:0] inputs. This provides the user with
3-level inputs for skew and PLL range control frequency multiplication from 1 to 12 without using divided
3-level inputs for feedback divide selection multiply / outputs for feedback.
divide ratios of (1-6, 8, 10, 12) / (2, 4) When the sOE pin is held low, all the outputs are synchro-
PLL bypass for DC testing nously enabled. However, if sOE is held high, all the outputs
External feedback, internal loop filter except 2Q0 and 2Q1 are synchronously disabled. The LOCK
12mA balanced drive outputs output asserts to indicate when Phase Lock has been achieved.
Low Jitter: <100ps cycle-to-cycle Furthermore, when PE is held high, all the outputs are synchro-
Power-down mode nized with the positive edge of the REF clock input. When PE is
Lock indicator held low, all the outputs are synchronized with the negative edge
Available in TQFP package of REF. The IDT5V995 has LVTTL outputs with 12mA balanced
Not Recommended for New Design drive outputs.
PE TEST FS LOCK
PD
sOE
FUNCTIONAL BLOCK DIAGRAM
3 3
REF
PLL
/ N
FB
3 3
DS1:0
3 1Q0
Skew
1F1:0
Select
3 1Q1
3 2Q0
Skew
2F1:0
Select
3 2Q1
3 3Q0
Skew
3F1:0
Select
3
3Q1
3 4Q0
Skew
4F1:0
Select
3 4Q1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDT / ICS PLL CLOCK DRIVER TURBOCLOCK II 1 IDT5V995 REV. B DECEMBER 20, 2013IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
(1)
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Symbol Description Max Unit
VDDQ, VDD Supply Voltage to Ground 0.5 to +4.6 V
VI DC Input Voltage 0.5 to VDD+0.5 V
42 38 37 36 34
44 43 41 40 39 35
REF Input Voltage 0.5 to +5.5 V
4F1 1
33 1F0
Maximum Power TA = 85C 0.7 W
sOE 2 DS1
32
Dissipation TA = 55C 1.1
PD 3 31 DS0
TSTG Storage Temperature Range 65 to +150 C
PE LOCK
4 30
NOTE:
VDDQ 5 29 VDDQ
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause per-
VDDQ
VDDQ 6 28
manent damage to the device. These are stress ratings only, and functional operation of
4Q1 27 1Q0
7 the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute-maximum-rated condi-
4Q0 26 1Q1
8
tions for extended periods may affect device reliability.
25 GND
GND 9
24 GND
GND 10
CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
23
GND GND
11
12 13 14 15 16 17 18 19 20 21 22
Parameter Description Typ. Max. Unit
CINInput Capacitance 5 7 pF
NOTE:
1. Capacitance applies to all inputs except TEST, FS, nF[1:0], and DS[1:0].
TQFP
TOP VIEW
PIN DESCRIPTION
Pin Name Type Description
REF IN Reference Clock Input
FB IN Feedback Input
(1)
TEST IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control
Summary Table) remain in effect. Set LOW for normal operation.
(1)
sOE IN Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and
2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0]
pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull
down).
PE IN Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of
the
reference clock (has internal pull-up).
nF[1:0] IN 3-level inputs for selecting 1 of 9 skew taps or frequency functions
FS IN Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)
nQ[1:0] OUT Four banks of two outputs with programmable skew
DS[1:0] IN 3-level inputs for feedback divider selection
PD IN Power down control. Shuts off entire chip when LOW (has internal pull-up).
LOCK OUT PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized
to
the inputs. (For more information on application specific use of the LOCK pin, please see AN237.)
VDDQ PWR Power supply for output buffers
NOTE:V DD1. When TESTPWR = MID and sOEPower supply for phase locked loop, lock output, and other internal circuitry = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in
effect unless nF[1:0] = LL.
GND PWR Ground
IDT / ICS PLL CLOCK DRIVER TURBOCLOCK II 2 IDT5V995 REV. B DECEMBER 20, 2013
GND 4F0
3Q1 3F1
3Q0 3F0
VDDQ FS
VDDQ
VDD
FB REF
VDDQ GND
VDDQ TEST
2Q1 2F1
2F0
2Q0
GND 1F1