VersaClock Programmable Clock 5X35023 Datasheet Generator Description Features Configurable OE pin function as OE, PD , PPS or DFC control The 5X35023 is the latest VersaClock programmable clock function generator with an integrated crystal, and is designed for low power, consumer, and high-performance PCI Express Configurable PLL bandwidth minimizes jitter peaking applications. PPS: Proactive Power Saving features save power during the end device power down mode The 5X35023 device is a 3 PLL architecture design, and each PLL is individually programmable allowing for up to 6 unique PPB: Performance-Power Balancing feature allows minimum frequencies outputs. The device has built-in unique features such power consumption base on required performance as Proactive Power Saving (PPS), Performance-Power Balancing DFC: Dynamic Frequency Control feature allows up to 4 (PPB), Overshoot Reduction Technology (ORT) and Extreme Low difference frequencies to switch dynamically Power DCO. Spread spectrum clock support to lower system EMI 2 An internal OTP memory allows the user to store the configuration I C interface in the device, after power up, user can change the register setting Integrated crystal 2 2 through the I C interface when I C mode is selected. The device has programmable VCO and PLL source selection to allow Key Specifications power-performance optimization base on the application requirements. The device supports 3 single-ended outputs and PCIe clocks phase jitter: PCIe Gen3 two pairs of differential outputs that support LVCMOS, LVPECL, Differential clocks < 3 ps rms jitter integer range 12kHz20MHz LVDS and LP-HCSL. Output Features Low Power 32.768kHz clock is supported with only less than 2 A current consumption for system RTC reference clock. 2 DIFF outputs with configurable LPHSCL, LVDS, LVPECL, LVCMOS output pairs. 1MHz500MHz (160MHz with LVCMOS Typical Applications mode at DIFF T) 3 LVCMOS outputs: 1MHz160MHz PCIe Gen1/2/3 clock generator Maximum 8 LVCMOS outputs as REF + 3 SE + 2 DIFF T Consumer application crystal replacements as LVCMOS SmartDevice, Handheld, Computing and Consumer Low Power 32.768kHz clock supported for all SE1SE3 applications Block Diagram OSC REF VDDDIFF1 Programmable DIFF1 Load Capacitor DIFF1B VDDDIFF2 PLL1 SEL DFC/ SCL DFC1 DIFF2 SDA DFC0 DIFF2B VDDSE1 Mux PLL2 SE1 & Divider OE1 Calibration VDDSE2 SE2 PLL3 VDD33 OE2 32.768K VDDA VDDSE3 DCO SE3 VBAT OE3 2019 Integrated Device Technology, Inc. 1 October 28, 20195X35023 Datasheet Contents Description 1 Typical Applications . 1 Features 1 Key Specifications 1 Output Features 1 Block Diagram . 1 Pin Assignments 3 Pin Descriptions 3 Detailed Functional Block Diagram . 4 Power Group 5 Output Sources 5 Output Source Selection Register Settings . 5 Absolute Maximum Ratings . 7 Thermal Characteristics 7 Recommended Operating Conditions . 7 Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down 8 Electrical Characteristics . 8 Electrical Characteristics VDDDIFF 9 Electrical Characteristics VDDSE 12 AC Electrical Characteristics . 14 Spread Spectrum Generation Specifications . 15 Glossary of Features . 15 Device Features and Functions . 16 DFCDynamic Frequency Control 16 DFC Function Programming . 17 PPSProactive Power Saving Function 17 PPS Function Programming . 18 Timer Function Description 18 OE Pin Function 18 Spread Spectrum . 20 VBAT . 21 ORTVCO Overshoot Reduction Technology . 21 PLL Features and Descriptions . 21 Output Clock Test Conditions . 22 I2C Bus Characteristics . 23 General I2C Mode Operations 24 Package Outline Drawings . 38 Marking Diagrams . 38 Ordering Information . 38 Revision History . 39 2019 Integrated Device Technology, Inc. 2 October 28, 2019