6P40368NDGI8 Renesas

Clock Generator for Wireless 6P40368 Datasheet Charge Module Description Features The 6P40368 is a small form factor clock generator with integrated No input clock source requirement crystal that is intended for low-power, consumer, wearable and smart Dynamic Frequency Control (DFC) is used for output frequency devices. selection 1.8V operating voltage The device is designed to support a single 1.8V LVCMOS clock 2 output and a dynamic frequency control for two frequency options. I C interface The frequency can be selected by one output pin. The 6P40368 has 2.5 2.5 mm 12-DFN package, small form factor an embedded crystal to offer a more reliable clock source with small board space requirements. Typical Applications Wireless charge module Block Diagram Figure 1. Block Diagram Power Monitor VDD1 8 POR OSC PLL2 CLKOUT VDDO DFC1 Overshoot Reduction 2 I C Engine (ORT) VSS DFC0 Pin Assignments Figure 2. Pin Assignments for 2.5 2.5 mm 12-DFN Package DFC0 1 12 V SS SEL DFC/DFC1 2 11 NC VSS 3 10 VDDOUT2 VSS 4 9 NC V 5 8 NC DD1 8 V CLKOUT DDOUT1 6 7 2.5 2.5 mm 12-DFN 2018 Integrated Device Technology, Inc. 1 August 16, 20186P40368 Datasheet Pin Descriptions Table 1. Pin Descriptions Number Name Type Description 1 DFC0 Input Dynamic frequency control pin. 2 SEL DFC/DFC1 Input Dynamic frequency control pin selected by SEL DFC at power-on default. 3V Power Ground pin. SS 4V Power Ground pin. SS 5V Power 1.8V power rail. DD1 8 6V Power Power supply pin for OUT1 output (1.8V). DDOUT1 7 CLKOUT Output 1.8V LVCMOS clock output. 8 NC No connect. 9 NC No connect. 10 V Power Output clock power supply pin 1.8V. DDOUT2 11 NC No connect. 12 V Power Ground pin. SS Frequency Selection Table 2: Frequency Selection SEL DFC DFC1 DFC0 CLKOUT (MHz) 0 0 0 6.16791 0 0 1 6.1298496 01 0 N/A 01 1 N/A 1x x x ORT VCO Overshoot Reduction Technology The 6P40368 supports the VCO overshoot reduction technology to prevent an output clock frequency spike when the device is changing frequency on-the-fly or doing DFC (Dynamic Frequency Control) function. The VCO frequency changes are controlled instead of free-run to targeted frequency. Output Clock Test Conditions Figure 3. LVCMOS Output Clock Test Condition 50 ohm 33 ohm 2 inches 2pF LVCMOS 2018 Integrated Device Technology, Inc. 2 August 16, 2018