DATASHEET 6-OUTPUT DB800ZL DERIVATIVE WITH INTEGRATED 85OHM TERMINATIONS IDT6V61036 General Description Features/Benefits The IDT6V61036 is a low-power 6-output differential buffer Low-Power-HCSL outputs w/Zo = 85 save power and that meets all the performance requirements of the Intel board space - no termination resistors required. Ideal for DB1200Z specification. It consumes 50% less power than blade servers. standard HCSL devices and has internal terminations to Space-saving 40-pin VFQFPN package allow direct connection to 85 ohm transmission lines. It is Fixed feedback path for 0ps input-to-output delay suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, 6 OE pins/Hardware control of each output and uses a fixed external feedback to maintain low drift for PLL or bypass mode PLL can dejitter incoming clock demanding QPI/UPI applications. Selectable PLL bandwidth minimizes jitter peaking in downstream PLL s Recommended Application Spread Spectrum Compatible tracks spreading input Buffer for Romley, Grantley and Purley Servers, SSDs and clock for low EMI PCIe Key Specifications Output Features Cycle-to-cycle jitter <50ps 6 - LP-HCSL Output Pairs w/integrated terminations (Zo = 85 ) Output-to-output skew <65ps Input-to-output delay variation <50ps PCIe Gen3 phase jitter <1.0ps RMS QPI/UPI 9.6GT/s 12UI phase jitter <0.2ps RMS Block Diagram OE(5:0) DFB OUT NC Z-PLL (SS Compatible) DIF IN DIF(5:0) DIF IN HIBW BYPM LOBW CKPWRGD/PD Logic SMBDAT SMBCLK IDT 6-OUTPUT DB800ZL DERIVATIVE WITH INTEGRATED 85OHM TERMINATIONS 1 IDT6V61036 REV E 112015IDT6V61036 6-OUTPUT DB800ZL DERIVATIVE WITH INTEGRATED 85OHM TERMINATIONS Pin Configuration 40 39 38 37 36 35 34 33 32 31 VDDA136V610360 NC vHIBW BYPM LOBW 229 VDD CKPWRGD PD 328 vOE3 GND427 DIF 3 VDDR526 DIF 3 EPAD is GND DIF IN625 VDD DIF IN 724 DIF 2 SMBDAT DIF 2 823 SMBCLK922 vOE2 DFB OUT NC 10 21 VDD 11 12 13 14 15 16 17 18 19 20 40-VFQFPN prefix indicates internal Pull-Up Resistor v prefix indicates Internal Pull-Dow n Resistor v prefix indicates Interal Pull-Up/Dow n Resistor (biased to VDD/2) 5mm x 5mm 0.4mm pin pitch Power Management Table PLL STATE IF NOT IN DIF IN/ SMBus DIF(5:0)/ BYPASS CKPWRGD PD DIF IN EN bit DIF(5:0) MODE 0 X X Low/Low OFF 0 Low/Low ON 1 Running 1 Running ON PLL Operating Mode PLL Operating Mode Readback Table HiBW BypM LoBW MODE HiBW BypM LoBW Byte0, bit 7 Byte 0, bit 6 Low PLL Lo BW Low (Low BW) 0 0 Mid Bypass Mid (Bypass) 0 1 High PLL Hi BW High (High BW) 1 1 NOTE: PLL is OFF in Bypass Mode Tri-level Input Thresholds Power Connections Level Voltage Pin Number <0.8V Low VDD GND Description Mid 1.2<Vin<1.8V 141 Analog PLL High Vin > 2.2V 5 4 Analog Input 12,16,20,24,27 IDT6V61036 SMBus Address 41 DIF clocks ,31,32,36,40 1101100 + Read/Write bit IDT 6-OUTPUT DB800ZL DERIVATIVE WITH INTEGRATED 85OHM TERMINATIONS 2 IDT6V61036 REV E 112015 DFB OUT NC NC VDD VDD vOE0 vOE5 DIF 0 DIF 5 DIF 0 DIF 5 VDD VDD DIF 1 DIF 4 DIF 1 DIF 4 vOE1 vOE4 VDD VDD