Clk 71V2546S 128K x 36 3.3V Synchronous ZBT SRAM 2.5V I/O, Burst Counter Pipelined Outputs Features 4-word burst capability (interleaved or linear) 128K x 36 memory configurations Individual byte write (BW1 - BW4) control (May tie active) Supports high performance system speed - 150 MHz Three chip enables for simple depth expansion (3.8 ns Clock-to-Data Access) TM 3.3V power supply (5%), 2.5V I/O Supply (VDDQ) ZBT Feature - No dead cycles between write and read Packaged in a JEDEC standard 100-pin plastic thin quad cycles flatpack (TQFP) and 119 ball grid array (BGA) Internally synchronized output buffer enable eliminates the Industrial temperature range (40C to +85C) is available need to control OE for selected speeds Single R/W (READ/WRITE) control pin Green parts available, see ordering information Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications Functional Block Diagram 128Kx36 BIT LBO MEMORY ARRAY Address A 0:16 DQ Address CE1, CE, CE2 R/W DQ Control CEN ADV/LD DI DO BWx DQ Control Logic Clk Mux Sel D Output Register Clock Q Gate OE 5294 drw 01a Data I/O 0:31 , I/O P 1:4 ZBT and ZeroBus Turnaround are trademarks of Renesas and the architecture is supported by Micron Technology and Motorola Inc. 1 Aug.12.20 Input Register71V2546, 128K x 36, 3.3V Synchronous ZBT SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges There are three chip enable pins (CE1, CE2, CE2) that allow the user Description to deselect the device when desired. If any one of these three are not The IDT71V2546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) asserted when ADV/LD is low, no new memory operation can be initiated. synchronous SRAM. It is designed to eliminate dead bus cycles when However, any pending data transfers (reads or writes) will be completed. turning the bus around between reads and writes, or writes and reads. TM The data bus will tri-state two cycles after chip is deselected or a write is Thus, they have been given the name ZBT , or Zero Bus Turnaround. initiated. Address and control signals are applied to the SRAM during one clock The IDT71V2546 has an on-chip burst counter. In the burst mode, the cycle, and two cycles later the associated data cycle occurs, be it read IDT71V2546 can provide four cycles of data for a single address or write. presented to the SRAM. The order of the burst sequence is defined by the The IDT71V2546 contains data I/O, address and control signal LBO input pin. The LBO pin selects between linear and interleaved burst registers. Output enable is the only asynchronous signal and can be used sequence. The ADV/LD signal is used to load a new external address to disable the outputs at any given time. (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = A Clock Enable (CEN) pin allows operation of the IDT71V2546 to be HIGH). suspended as long as necessary. All synchronous inputs are ignored The IDT71V2546 SRAM utilizes a high-performance CMOS process when (CEN) is high and the internal device registers will hold their previous and is packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic values. quad flatpack (TQFP) as well as a 119 ball grid array (BGA). Pin Description Summary A0-A16 Address Inputs Isnput Synchronou Chip Enables Isnput Synchronou CE1, CE2, CE2 OE Output Enable Isnput Asynchronou R/W Read/Write Signal Isnput Synchronou Clock Enable Isnput Synchronou CEN BW1, BW2, BW3, BW4 Individual Byte Write Selects Isnput Synchronou CkLK Cloc IAnput N/ ADV/LD Advance burst address / Load new address Isnput Synchronou Linear / Interleaved Burst Order Icnput Stati LBO ZeZ Sleep Mod Isnput Synchronou I/O0-I/O31, I/OP1-I/OP4 Data Input / Output Is/O Synchronou VDD, VDDQ Core Power, I/O Power Scupply Stati VSS Ground Scupply Stati 5294 tbl 01 6.422 Aug.12.20