Clk 128K x 36, 3.3V Synchronous IDT71V546S SRAM with ZBT Feature Burst Counter and Pipelined Outputs Features 128K x 36 memory configuration, pipelined outputs Positive clock-edge triggered address, data, and control Supports high performance system speed - 133 MHz signal registers for fully pipelined applications (4.2 ns Clock-to-Data Access) 4-word burst capability (interleaved or linear) TM ZBT Feature - No dead cycles between write and read Individual byte write (BW1 - BW4) control (May tie active) cycles Three chip enables for simple depth expansion Internally synchronized registered outputs eliminate the Single 3.3V power supply (5%) need to control OE Packaged in a JEDEC standard 100-pin TQFP package Single R/W (READ/WRITE) control pin Green parts available, see Ordering Information Functional Block Diagram 128K x 36 BIT LBO MEMORY ARRAY Address A 0:16 DQ Address CE1, CE2, CE2 R/W DQ Control CEN ADV/LD DI DO BWx DQ Control Logic Clk Mux Sel D Output Register Clock Q Gate OE 3821 drw 01 . Data I/O 0:31 , I/O P 1:4 AUGUST 2017 ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc. 1 DSC-3821/07 2017 Integrated Device Technology, Inc. Input RegisterIDT71V546, 128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges Description There are three chip enable pins (CE1, CE2, CE2) that allow the user The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) to deselect the device when desired. If any one of these three is not active synchronous SRAM organized as 128K x 36 bits. It is designed to when ADV/LD is low, no new memory operation can be initiated and any eliminate dead bus cycles when turning the bus around between reads burst that was in progress is stopped. However, any pending data TM and writes, or writes and reads. Thus it has been given the name ZBT , transfers (reads or writes) will be completed. The data bus will tri-state two or Zero Bus Turn-around. cycles after the chip is deselected or a write initiated. Address and control signals are applied to the SRAM during one The IDT71V546 has an on-chip burst counter. In the burst mode, the clock cycle, and two cycles later its associated data cycle occurs, be it IDT71V546 can provide four cycles of data for a single address presented read or write. to the SRAM. The order of the burst sequence is defined by the LBO input The IDT71V546 contains data I/O, address and control signal regis- pin. The LBO pin selects between linear and interleaved burst sequence. ters. Output enable is the only asynchronous signal and can be used to The ADV/LD signal is used to load a new external address (ADV/LD = disable the outputs at any given time. LOW) or increment the internal burst counter (ADV/LD = HIGH). A Clock Enable (CEN) pin allows operation of the IDT71V546 to be The IDT71V546 SRAM utilizes a high-performance, high-volume suspended as long as necessary. All synchronous inputs are ignored 3.3V CMOS process, and is packaged in a JEDEC standard 14mm x when CEN is high and the internal device registers will hold their previous 20mm 100- pin thin plastic quad flatpack (TQFP) for high board density. values. Pin Description Summary A0 - A16 Address Inputs Input Synchronous Three Chip Enables Input Synchronous CE1, CE2, CE2 OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous Individual Byte Write Selects Input Synchronous BW1, BW2, BW3, BW4 CLK Clock Input N/A ADV/LD Advance Burst Address / Load New Address Input Synchronous Linear / Interleaved Burst Order Input Static LBO I/O0 - I/O31, I/OP1 - I/OP4 Data Input/Output I/O Synchronous VDD 3.3V Power Supply Static VSS Ground Supply Static 3821 tbl 01 2