74FCT3807SPGGI8 Renesas

Low Skew 1 to 10 Clock Buffer 74FCT3807S DATASHEET Description Features The 74FCT3807S is a low skew, single input to ten output, Low additive phase jitter RMS: 50fs clock buffer. The 74FCT3807S has best in class additive Low skew outputs (50ps) phase Jitter of sub 50 fsec. Packaged in 20-pin TSSOP, SSOP, QSOP and VFQFPN packages, Pb (lead) free IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Operating voltages of 1.8V to 3.3V Contact us for all of your clocking needs. Input/Output clock frequency up to 200 MHz Advanced, low power CMOS process Extended temperature range (-40C to +105C) Block Diagram Q0 Q1 Q2 Q3 Q4 ICLK Q5 Q6 Q7 Q8 Q9 74FCT3807S REVISION A 03/18/15 1 2015 Integrated Device Technology, Inc.74FCT3807S DATASHEET Pin Assignments ICLK 1 20 VDD 19 18 17 16 20 2 19 GND Q9 ICLK 1 15 VDD Q0 3 18 Q8 2 14 GND Q6 4 17 GND VDD Q1 Q7 5 16 EPAD 3 13 Q0 GND 6 15 VDD GND 4 12 VDD Q5 Q2 7 14 Q6 5 11 Q1 Q4 VDD 8 13 GND 6 7 8 910 9 12 Q3 Q5 10 11 Q4 GND 20-pin VFQFPN 20-pin TSSOP/SSOP/QSOP Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 ICLK Input Clock input. 2 GND Power Connect to ground. 3 Q0 Output Clock output 0. 4 VDD Power Connect to +1.8V, +2.5 V, or +3.3 V. 5 Q1 Output Clock output 1. 6 GND Power Connect to ground. 7 Q2 Output Clock Output 2. 8 VDD Power Connect to +1.8V, +2.5 V, or +3.3 V. 9 Q3 Output Clock Output 3. 10 GND Power Connect to ground. 11 Q4 Output Clock Output 4. 12 Q5 Output Clock Output 5. 13 GND Power Connect to ground. 14 Q6 Output Clock Output 6. 15 VDD Power Connect to +1.8V, +2.5 V, or +3.3 V. 16 Q7 Output Clock Output 7. 17 GND Power Connect to ground. 18 Q8 Output Clock Output 8. 19 Q9 Output Clock Output 9. 20 VDD Power Connect to +1.8V, +2.5 V, or +3.3 V. LOW SKEW 1 TO 10 CLOCK BUFFER 2 REVISION A 03/18/15 GND VDD Q2 Q9 VDD Q8 Q3 GND GND Q7