IDT74FCT88915TT COMMERCIAL TEMPERATURE RANGE LOW SKEW PLL-BASED CMOS CLOCK DRIVER LOW SKEW PLL-BASED IDT74FCT88915TT CMOS CLOCK DRIVER 55/70/100/133 NRND Product Assembled Product Discontinuance Notice Last Time Buy Expires on (9/25/2013) from Die Bank Only FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology The FCT88915TT uses phase-lock loop technology to lock the frequency Input frequency range: 10MHz f2Q Max. spec and phase of outputs to the input reference clock. It provides low skew clock (FREQ SEL = HIGH) distribution for high performance PCs and workstations. One of the outputs is Max. output frequency: 133MHz fed back to the PLL at the FEEDBACK input resulting in essentially zero delay Pin and function compatible with MC88915 across the device. The PLL consists of the phase/frequency detector, charge Five non-inverting outputs, one inverting output, one 2x pump, loop filter and VCO. The VCO is designed to run optimally between output, one 2 output all outputs are TTL-compatible 20MHz and f2Q Max. Output Skew < 500ps (max.) The FCT88915TT provides eight outputs with 500ps skew. The Q5 output is Duty cycle distortion < 500ps (max.) inverted from the Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs Part-to-part skew: 0.55ns (from tPD max. spec) at half the Q frequency. 64/15mA drive at TTL output voltage levels The FREQ SEL control provides an additional 2 option in the output path. Available in PLCC and SSOP packages PLL EN allows bypassing of the PLL, which is useful in static test modes. When Not Recommended for New Design PLL EN is low, SYNC input may be used as a test clock. In this test mode, the input frequency is not limited to the specified range and the polarity of outputs is complementary to that in normal operation (PLL EN = 1). The LOCK output attains logic high when the PLL is in steady-state phase and frequency lock. The FCT88915TT requires external loop filter components as recom- mended in Figure 2. FUNCTIONAL BLOCK DIAGRAM FEEDBACK LOCK Voltage 0 Phase/Freq. SYNC (0) M Controlled Charge Pump Detector u Oscilator x 1 SYNC (1) LF REF SEL 01 2Q PLL EN Mux ( 1) 1 M Q0 DD QQ u CPCP QQ R Divide ( 2) x 0 -By-2 Q1 D Q FREQ SEL CP R RST Q2 D Q CP R D Q3 Q CP R D Q Q4 CP R Q5 D Q CP R Q/2 D Q CP R The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE MAY 2013 1 2013 Integrated Device Technology, Inc. DSC-4245/4IDT74FCT88915TT COMMERCIAL TEMPERATURE RANGE LOW SKEW PLL-BASED CMOS CLOCK DRIVER PIN CONFIGURATIONS 1 28 Q4 GND 43 21 28 27 26 Q5 2 27 VCC FEEDBK 25 Q/2 5 3 VCC 26 2Q 4 REF SEL 24 GND RST 25 Q/2 6 5 24 FEEDBACK GND 23 Q3 SYNC(0) 7 6 23 REF SEL Q3 VCC(AN) 8 22 VCC 7 VCC SYNC(0) 22 8 VCC(AN) 21 Q2 LF 9 21 Q2 9 LF 20 GND 10 GND GND(AN) 20 GND(AN) 10 19 LOCK SYNC(1) 11 18 PLL EN SYNC(1) 11 19 LOCK 12 17 FREQ SEL GND 12 13 14 15 16 17 18 GND 13 16 Q1 14 15 VCC Q0 PLCC SSOP TOP VIEW TOP VIEW PIN DESCRIPTION Pin Name I/O Description SYNC(0) I Reference clock input SYNC(1) I Reference clock input REF SEL I Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram) FREQ SEL I Selects between 1 and 2 frequency options (refer to functional block diagram) FEEDBACK I Feedback input to phase detector LF I Input for external loop filter connection Q0-Q4 O Clock outputs Q5 O Inverted clock output 2Q O Clock output (2 x Q frequency) Q/2 O Clock output (Q frequency 2) LOCK O Indicates phase lock has been achieved (HIGH when locked) RST I Asynchronous reset (active LOW) PLL EN I Disables phase-lock for low frequency testing (refer to functional block diagram) 2 FREQ SEL RST GND VCC Q5 Q0 GND VCC Q4 Q1 VCC GND 2Q PLL EN