IDT74LVCH162373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74LVCH162373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: DESCRIPTION: Typical tSK(o) (Output Skew) < 250ps The LVCH162373A 16-bit transparent D-type latch is built using ad- ESD > 2000V per MIL-STD-883, Method 3015 > 200V using vanced dual metal CMOS technology. This high-speed, low-power latch machine model (C = 200pF, R = 0) is ideal for temporary storage of data. The LVCH162373A can be used for VCC = 3.3V 0.3V, Normal Range implementing memory address latches, I/O ports, and bus drivers. The VCC = 2.7V to 3.6V, Extended Range output enable and latch enable controls are organized to operate each CMOS power levels (0.4 W typ. static) device as two 8-bit latches or one 16-bit latch. Flow-through organization All inputs, outputs, and I/O are 5V tolerant of signal pins simplifies layout. All inputs are designed with hysteresis for Available in TSSOP package improved noise margin. All pins of the LVCH162373A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed DRIVE FEATURES: 3.3V/5V supply system. Balanced Output Drivers: 12mA The LVCH162373A has series resistors in the device output structure Low switching noise which will significantly reduce line noise when used with light loads. The driver has been developed to drive 12mA at the designated threshold APPLICATIONS: levels. 5V and 3.3V mixed voltage systems The LVCH162373A has bus-hold which retains the inputs last state Data communication and telecommunication systems whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. FUNCTIONAL BLOCK DIAGRAM 24 1 1OE 2OE 25 48 2LE 1LE 47 36 D D 2D1 1D1 13 2 1Q1 C 2Q1 C TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS INDUSTRIAL TEMPERATURE RANGE OCTOBER 2015 1 DSC-4888/5IDT74LVCH162373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND 0.5 to +6.5 V TSTG Storage Temperature 65 to +150 C 1LE 1OE 1 48 IOUT DC Output Current 50 to +50 mA 2 1D1 1Q1 47 IIK Continuous Clamp Current, 50 mA 1D2 IOK VI < 0 or VO < 0 1Q2 3 46 ICC Continuous Current through each 100 mA GND GND 4 45 ISS VCC or GND 5 NOTE: 1D3 1Q3 44 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause 6 1D4 permanent damage to the device. This is a stress rating only and functional operation 1Q4 43 of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating 7 VCC VCC 42 conditions for extended periods may affect reliability. 8 1Q5 41 1D5 1Q6 9 40 1D6 10 GND 39 GND CAPACITANCE (TA = +25C, F = 1.0MHz) 11 1D7 38 (1) 1Q7 Symbol Parameter Conditions Typ. Max. Unit 1D8 12 CIN Input Capacitance VIN = 0V 4.5 6 pF 1Q8 37 COUT Output Capacitance VOUT = 0V 6.5 8 pF 2D1 13 2Q1 36 CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF 14 2D2 2Q2 35 NOTE: 1. As applicable to the device type. 15 GND 34 GND 16 33 2D3 2Q3 PIN DESCRIPTION 17 32 2D4 2Q4 Pin Names Description 18 31 VCC VCC (1) xDx Data Inputs 19 30 2D5 2Q5 xLE Latch Enable Inputs (Active HIGH) x Q x 3-State Outputs 20 29 2D6 2Q6 xOE Output Enable Inputs (Active LOW) 21 GND GND 28 NOTE: 22 1. These pins haveBus-Hol. All other pins are standard inputs, outputs, or I/Os. 2D7 27 2Q7 23 2D8 26 2Q8 (1) 24 2LE 2OE 25 FUNCTION TABLE (EACH 8-BIT SECTION) Inputs Outputs xOE xLE xDx xQx LH H H TSSOP TOP VIEW LH L L (2) LL X Q HX X Z NOTES: 1. H = HIGH Voltage Level X = Dont Care L = LOW Voltage Level Z = High-Impedance 2. Output level before the indicated steady-state input conditions were established. 2