74LVCH162374APAG Renesas

IDT74LVCH162374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74LVCH162374A EDGE TRIGGERED D-TYPE FLIP- FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD DESCRIPTION: FEATURES: Typical tSK(o) (Output Skew) < 250ps The LVCH162374A 16-bit edge-triggered D-type flip-flop is built using ESD > 2000V per MIL-STD-883, Method 3015 > 200V using advanced dual metal CMOS technology. This high-speed, low-power machine model (C = 200pF, R = 0) register is ideal for use as a buffer register for data synchronization and VCC = 3.3V 0.3V, Normal Range storage. The output enable (OE) and clock (CLK) controls are organized VCC = 2.7V to 3.6V, Extended Range to operate each device as two 8-bit registers or one 16-bit register with CMOS power levels (0.4 W typ. static) common clock. Flow-through organization of signal pins simplifies layout. All inputs, outputs, and I/O are 5V tolerant All inputs are designed with hysteresis for improved noise margin. Available in TSSOP package All pins of the LVCH162374A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. DRIVE FEATURES: The LVCH162374A has series resistors in the device output structure Balanced Output Drivers: 12mA which will significantly reduce line noise when used with light loads. This Low switching noise driver has been developed to drive 12mA at the designated thresholds. The LVCH162374A has bus-hold which retains the inputs last state APPLICATIONS: whenever the input goes to a high impedance. This prevents floating inputs 5V and 3.3V mixed voltage systems and eliminates the need for pull-up/down resistors. Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1 24 2OE 1OE 48 25 1CLK 2CLK 47 36 1D1 2D1 1D 1D 2 13 C1 2Q1 1Q1 C1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2015 1 2015 Integrated Device Technology, Inc. DSC-4678/5IDT74LVCH162374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND 0.5 to +6.5 V TSTG Storage Temperature 65 to +150 C 1CLK 1 48 1OE IOUT DC Output Current 50 to +50 mA 2 1D1 1Q1 47 IIK Continuous Clamp Current, 50 mA 1D2 IOK VI < 0 or VO < 0 1Q2 3 46 ICC Continuous Current through each 100 mA GND 4 45 GND ISS VCC or GND 5 1D3 1Q3 44 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause 6 1D4 1Q4 permanent damage to the device. This is a stress rating only and functional operation 43 of the device at these or any other conditions above those indicated in the operational VCC 7 VCC 42 sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 8 1D5 1Q5 41 1D6 9 40 1Q6 GND 10 GND 39 CAPACITANCE (TA = +25C, F = 1.0MHz) 11 38 1D7 1Q7 (1) Symbol Parameter Conditions Typ. Max. Unit 1D8 12 1Q8 37 CIN Input Capacitance VIN = 0V 4.5 6 pF 2D1 13 2Q1 36 COUT Output Capacitance VOUT = 0V 6.5 8 pF 2D2 14 2Q2 CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF 35 NOTE: GND GND 15 34 1. As applicable to the device type. 16 33 2D3 2Q3 17 32 2D4 2Q4 PIN DESCRIPTION 18 31 VCC VCC Pin Names Description 19 30 2D5 2Q5 (1) xDx Data Inputs 20 29 2D6 xCLK Clock Inputs 2Q6 x Q x 3-State Outputs 21 GND GND 28 xOE 3-State Output Enable Inputs (Active LOW) 22 2D7 27 2Q7 NOTE: 23 2D8 1. These pins haveBus-Hol. All other pins are standard inputs, outputs, or I/Os. 26 2Q8 24 2CLK 2OE 25 (1) FUNCTION TABLE (EACH FLIP-FLOP) Inputs Outputs TSSOP TOP VIEW xOE xCLK xDx xQx L HH L LL (2) L H or L X Q HX X Z NOTES: 1. H = HIGH Voltage Level X = Dont Care L = LOW Voltage Level Z = High-Impedance 2. Output level before the indicated steady-state input conditions were established. 2