OCTAL T1/E1 SHORT HAUL IDT82V2048 LINE INTERFACE UNIT FEATURES Low impedance transmit drivers with high-Z Fully integrated octal T1/E1 short haul line interface which supports 100 T1 twisted pair, 120 E1 twisted pair and 75 Selectable hardware and parallel/serial host interface E1 coaxial applications Local, Remote and Inband Loopback test functions Selectable Single Rail mode or Dual Rail mode and AMI or Hitless Protection Switching (HPS) for 1 to 1 protection without B8ZS/HDB3 encoder/decoder relays Built-in transmit pre-equalization meets G.703 & T1.102 JTAG boundary scan for board test Selectable transmit/receive jitter attenuator meets ETSI CTR12/ 3.3 V supply with 5 V tolerant I/O 13, ITU G.736, G.742, G.823 and AT&T Pub 62411 specifications Low power consumption SONET/SDH optimized jitter attenuator meets ITU G.783 Operating temperature range: -40C to +85C mapping jitter specification Available in 144-pin Thin Quad Flat Pack (TQFP) and 160-pin Digital/Analog LOS detector meets ITU G.775, ETS 300 233 and Plastic Ball Grid Array (PBGA) packages T1.231 Green package options available ITU G.772 non-intrusive monitoring for in-service testing for any one of channel 1 to channel 7 FUNCTIONAL BLOCK DIAGRAM One of Eight Identical Channels LOS LOSn Detector CLK&Data B8ZS/ RTIPn RCLKn Jitter Recovery Slicer HDB3/AMI RDn/RDPn Attenuator RRINGn CVn/RDNn (DPLL) Decoder IBLC Analog Peak Digital Remote Detector Loopback Detector Loopback Loopback AIS Detector B8ZS/ TTIPn TCLKn Line Waveform Jitter HDB3/AMI TDn/TDPn Driver Shaper Attenuator TRINGn BPVIn/TDNn Encoder IBLC Generator Transmit All Ones VDDIO Register G.772 Clock VDDT Control Interface JTAG TAP File Monitor Generator VDDD VDDA Figure-1 Block Diagram November 14, 2012 IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 2010- Integrated Device Technology, Inc. DSC-6037/19 MCLK OE CLKE MODE 2:0 CS/JAS TS2/SCLK/ALE/AS TS1/RD/R/W TS0/SDI/WR/DS SDO/RDY/ACK INT LP 7:0 /D 7:0 /AD 7:0 MC 3:0 /A 4:0 TRST TCK TMS TDI TDOIDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT INDUSTRIAL TEMPERATURE RANGES DESCRIPTION The IDT82V2048 is a single chip, 8-channel T1/E1 short haul PCM The IDT82V2048 offers hardware control mode and software control transceiver with a reference clock of 1.544 MHz (T1) or 2.048 MHz (E1). mode. Software control mode works with either serial host interface or The IDT82V2048 contains 8 transmitters and 8 receivers. parallel host interface. The latter works via an Intel/Motorola compatible 8-bit parallel interface for both multiplexed or non-multiplexed applica- All the receivers and transmitters can be programmed to work either tions. Hardware control mode uses multiplexed pins to select different in Single Rail mode or Dual Rail mode. B8ZS/HDB3 or AMI encoder/ operation modes when the host interface is not available to the device. decoder is selectable in Single Rail mode. Pre-encoded transmit data in NRZ format can be accepted when the device is configured in Dual Rail The IDT82V2048 also provides loopback and JTAG boundary scan mode. The receivers perform clock and data recovery by using inte- testing functions. Using the integrated monitoring function, the grated digital phase-locked loop. As an option, the raw sliced data (no IDT82V2048 can be configured as a 7-channel transceiver with non- retiming) can be output on the receive data pins. Transmit equalization is intrusive protected monitoring points. implemented with low-impedance output drivers that provide shaped The IDT82V2048 can be used for SDH/SONET multiplexers, central waveforms to the transformer, guaranteeing template conformance. office or PBX, digital access cross connects, digital radio base stations, A jitter attenuator is integrated in the IDT82V2048 and can be remote wireless modules and microwave transmission systems. switched into either the transmit path or the receive path for all channels. The jitter attenuation performance meets ETSI CTR12/13, ITU G.736, G.742, G.823, and AT&T Pub 62411 specifications. PIN CONFIGURATIONS BPVI3/TDN3 72 BPVI4/TDN4 109 71 RCLK3 110 RCLK4 RD3/RDP3 70 RD4/RDP4 111 CV3/RDN3 112 69 CV4/RDN4 LOS3 68 LOS4 113 RTIP3 114 67 OE 66 RRING3 CLKE 115 65 VDDT3 116 VDDT4 64 TTIP3 117 TTIP4 63 TRING3 TRING4 118 62 GNDT3 119 GNDT4 61 RRING2 RTIP4 120 60 RTIP2 121 RRING4 GNDT2 59 GNDT5 122 58 TRING2 123 TRING5 57 TTIP2 124 TTIP5 56 VDDT2 125 VDDT5 IDT82V2048 RTIP1 55 126 RRING5 54 RRING1 127 RTIP5 (Top View) VDDT1 53 128 VDDT6 52 TTIP1 129 TTIP6 TRING1 51 130 TRING6 50 GNDT1 131 GNDT6 RRING0 49 132 RTIP6 48 RTIP0 133 RRING6 GNDT0 47 134 GNDT7 46 TRING0 135 TRING7 TTIP0 45 136 TTIP7 44 VDDT0 137 VDDT7 MODE1 43 138 RRING7 42 LOS0 139 RTIP7 41 CV0/RDN0 140 LOS7 40 RD0/RDP0 141 CV7/RDN7 39 RCLK0 142 RD7/RDP7 38 BPVI0/TDN0 143 RCLK7 37 TD0/TDP0 144 BPVI7/TDN7 Figure-2 TQFP144 Package Pin Assignment 2 TD4/TDP4 TD7/TDP7 1 108 TCLK7 2 TCLK4 107 LOS5 LOS6 3 106 CV6/RDN6 4 CV5/RDN5 105 RD5/RDP5 RD6/RDP6 5 104 RCLK5 RCLK6 6 103 BPVI5/TDN5 BPVI6/TDN6 7 102 TD6/TDP6 8 TD5/TDP5 101 TCLK5 TCLK6 9 100 MCLK 10 TDI 99 TDO MODE2 11 98 TCK A4 12 97 TMS MC3/A3 13 96 TRST MC2/A2 14 95 IC MC1/A1 15 94 MC0/A0 16 IC 93 VDDIO VDDIO 17 92 GNDIO GNDIO 18 91 VDDA VDDD 19 90 GNDA GNDD 20 89 MODE0/CODE LP0/D0/AD0 21 88 CS/JAS LP1/D1/AD1 22 87 TS2/SCLK/ALE/AS LP2/D2/AD2 23 86 TS1/RD/R/W LP3/D3/AD3 24 85 TS0/SDI/WR/DS LP4/D4/AD4 25 84 SDO/RDY/ACK LP5/D5/AD5 26 83 INT LP6/D6/AD6 27 82 TCLK2 LP7/D7/AD7 28 81 TD2/TDP2 TCLK1 29 80 BPVI2/TDN2 TD1/TDP1 30 79 RCLK2 BPVI1/TDN1 31 78 RD2/RDP2 RCLK1 32 77 CV2/RDN2 RD1/RDP1 33 76 LOS2 CV1/RDN1 34 75 TCLK3 LOS1 35 74 TD3/TDP3 TCLK0 36 73