DUAL CHANNEL E1 IDT82V2052E SHORT HAUL LINE INTERFACE UNIT FEATURES: Dual channel E1 short haul line interfaces - PRBS (Pseudo Random Bit Sequence) generation and detection 15 Supports HPS (Hitless Protection Switching) for 1+1 protection with 2 -1 PRBS polynomials without external relays - 16-bit BPV (Bipolar Pulse Violation) / Excess Zero/ PRBS error Single 3.3 V power supply with 5 V tolerance on digital interfaces counter Meets or exceeds specifications in - Analog loopback, Digital loopback, Remote loopback - ANSI T1.102 Adaptive receive sensitivity up to -20 dB (Host Mode only) - ITU I.431, G.703, G.736, G.775 and G.823 Non-intrusive monitoring per ITU G.772 specification - ETSI 300-166, 300-233 and TBR12/13 Short circuit protection and internal protection diode for line Software programmable or hardware selectable on: drivers - Wave-shaping templates LOS (Loss Of Signal) detection with programmable LOS levels - Line terminating impedance (E1: 75 /120 ) (Host Mode only) - Adjustment of arbitrary pulse shape AIS (Alarm Indication Signal) detection - JA (Jitter Attenuator) position (receive path or transmit path) JTAG interface - Single rail/dual rail system interfaces Supports serial control interface, Motorola and Intel Non-Multi- - HDB3/AMI line encoding/decoding plexed interfaces and hardware control mode - Active edge of transmit clock (TCLK) and receive clock (RCLK) Pin compatible to 82V2082 T1/E1/J1 Long Haul/Short Haul LIU - Active level of transmit data (TDATA) and receive data (RDATA) and 82V2042E T1/E1/J1 Short Haul LIU - Receiver or transmitter power down Available in 80-pin TQFP - High impedance setting for line drivers Green package options available DESCRIPTION: The IDT82V2052E is a dual channel E1 Line Interface Unit. The according to the applications. Two different kinds of line terminating imped- IDT82V2052E performs clock/data recovery, AMI/HDB3 line decoding and ance, 75 and 120 are selectable on a per channel basis. The chip also detects and reports the LOS conditions. An integrated Adaptive Equalizer provides driver short-circuit protection and internal protection diode and is available to increase the receive sensitivity and enable programming of supports JTAG boundary scanning. The chip can be controlled by either LOS levels. In transmit path, there is an AMI/HDB3 encoder and Waveform software or hardware. Shaper. There is one Jitter Attenuator, which can be placed in either the The IDT82V2052E can be used in LAN, WAN, Routers, Wireless Base receive path or the transmit path. The Jitter Attenuator can also be disabled. Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, The IDT82V2052E supports both Single Rail and Dual Rail system inter- CSU/DSU equipment, etc. faces. To facilitate the network maintenance, a PRBS generation/detection circuit is integrated in the chip, and different types of loopbacks can be set .IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 December 12, 2005 2005 Integrated Device Technology, Inc. DSC-6779/1IDT82V2052E DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT FUNCTIONAL BLOCK DIAGRAM One of the Two Identical Channels LOSn LOS/AIS Detector RCLKn Data and Receiver Adaptive RTIPn Data HDB3/AMI Jitter Internal RDn/RDPn Clock Equalizer Slicer Attenuator Decoder Termination RRINGn CVn/RDNn Recovery PRBS Detector Remote Analog Digital Loopback Loopback Loopback TCLKn TTIPn Transmitter Jitter Line HDB3/AMI Waveform TDn/TDPn Internal Attenuator Driver Shaper TRINGn Decoder TDNn Termination PRBS Generator TAOS Clock Register Software Control Interface Pin Control JTAG TAP Generator Files G.772 Monitor VDDIO VDDD VDDA VDDT VDDR Figure-1 Block Diagram FUNCTIONAL BLOCK DIAGRAM 2 December 12, 2005 MCLK INT CS SDO SCLK R/W/WR/SDI RD/DS/SCLKE A 5:0 D 7:0 MODE 1:0 TERMn RXTXM 1:0 PULSn PATTn 1:0 JA 1:0 MONTn LPn 1:0 THZ RCLKE RPDn RST TRST TCK TMS TDI TDO