IDT82V3910 Synchronous Ethernet SETS Short Form Datasheet for 10GbE and 40GbE Provides OUT1 to OUT5 output CMOS clocks whose frequency FEATURES cover from 1PPS to 125 MHz HIGHLIGHTS Provides OUT6,OUT7,OUT10 and OUT11 output differential Jitter generation <0.3 ps RMS (10 kHz to 20 MHz), meets jitter gen- clocks whose frequency cover from 25 MHz to 644.53125 MHz eration requirements of leading PHYs supporting 10GBASE-R, Provides OUT8 for composite clocks and OUT9 for 1.544 MHz/ 10GBASE-W, 40GBASE-R, OC-192 and STM-64 2.048 MHz (BITS/SSU) Features 0.5 mHz to 35 Hz bandwidth Provides output clocks for BITS, GPS, 3G, GSM, etc. Provides node clock for ITU-T G.8261/G.8262 Synchronous Ether- Provides a 1PPS, 2 kHz, 4 kHz, or 8 kHz frame sync input signal, net (SyncE) and a 1PPS, 2 kHz or 8 kHz frame sync output signal Provides node clocks for Cellular and WLL base-station (GSM and Internal DCO can be controlled by an external processor to be used 3G networks) for IEEE-1588 clock generation Provides clocks for DSL access concentrators (DSLAM), especially Supports programmable input-to-output phase offset adjustment for Japan TCM-ISDN network timing based ADSL equipments Limits the phase and frequency offset of the outputs Provides clocks for 1 Gigabit, 10 Gigabit, and 40 Gigabit Ethernet Supports Forced or Automatic operating mode switch controlled by Supports clock generation for IEEE-1588 applications an internal state machine. Automatic mode switch supports Free- Run, Locked and Holdover modes MAIN FEATURES Supports manual and automatic selected input clock switch Provides an integrated solution for Synchronous Equipment Timing Supports automatic hitless selected input clock switch on clock fail- Source, including Stratum3, SMC, EEC-Option1 and EEC- ure Option 2 Clocks Supports three types of input clock sources: recovered clock from Integrates T4 DPLL and T0 DPLL T4 DPLL locks independently or STM-N or OC-n, PDH network synchronization timing and external locks to T0 DPLL synchronization reference timing Supports programmable DPLL bandwidth (0.5 mHz to 35 Hz) and Supports AMI, LVPECL/LVDS and CMOS input/output technologies damping factor (1.2 to 20 in 5 steps) Supports Master/Slave application (two chips used together) to -5 Supports 1.1X10 ppm absolute holdover accuracy and enable system protection against single chip failure -8 4.4X10 ppm instantaneous holdover accuracy Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE, Supports hitless reference switching to minimize phase transients ITU-T G.812, ITU-T G.8262, ITU-T G.813 and ITU-T G.783 Recom- on T0 DPLL output to be no more than 0.61 ns mendations Integrates 2 jitter attenuating APLLs to generate ultra-low jitter OTHER FEATURES clocks I2C Microprocessor interface Supports 3 clock modes: SONET, Ethernet, and Ethernet LAN- IEEE 1149.1 JTAG Boundary Scan PHY Single 3.3 V operation with 5 V tolerant CMOS I/Os Supports up to two crystal connections, allowing each APLL to 1mm ball pitch CABGA green package support up to two modes of operation Supports input and output clocks whose frequencies range from APPLICATIONS 1PPS to 644.53125 MHz SMC / SEC (SONET / SDH equipment) Includes 1PPS clock input and output EEC (Synchronous Ethernet equipment) Provides IN1 and IN2 for 64kHz+8kHz or Core and access IP switches / routers 64 kHz + 8 kHz + 0.4 kHz composite clocks Gigabit and Terabit IP switches / routers Provides IN3, IN4, IN7~IN14 input CMOS clocks whose frequen- Cellular and WLL base-station node clocks cies range from 1PPS to 156.25 MHz Broadband and multi-service access equipment Provides IN5 and IN6 input differential clocks whose frequencies range from 1PPS to 625 MHz IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 July 1, 2013 2013 Integrated Device Technology, Inc. DSC-7238/-IDT82V3910 DATASHEET SYNCHRONOUS ETHERNET SETS FOR 10GBE AND 40GBE DESCRIPTION The 82V3910 Synchronous Ethernet (SyncE) SETS meets the alone. In Locked mode the DPLLs filter reference clock jitter with the requirements of ITU-T G.8262/G.813 for EEC/SEC options 1 and 2 and selected bandwidth. In Locked mode the long-term DPLL frequency it meets the requirements of Telcordia GR-253-CORE Stratum 3 (S3) accuracy is the same as the long term frequency accuracy of the and SONET Minimum Clock (SMC). The 82V3910 ultra-low jitter output selected input reference. In Holdover mode the DPLL uses frequency clocks can be used to directly synchronize 10GBASE-R/10GBASE-W data acquired while in Locked mode to generate accurate frequencies and OC-192/STM-64 PHYs and 40GBASE-R PHYs in Synchronous when input references are not available. In DCO Control Mode the DPLL Ethernet and SONET/SDH equipment. control loop is opened and the DCO can be used by an algorithm (e.g. IEEE 1588 clock servo) running on an external processor to synthesize The Synchronous Equipment Timing Source (SETS) functions are clock signals. provided by two independent digital PLLs (DPLLs), T0 and T4, each with embedded clock synthesizers. The T0 DPLL meets the network syn- The 82V3910 requires a 12.8 MHz master clock for its reference chronization requirements for frequency accuracy, pull-in, hold-in, pull- monitors and other digital circuitry. The frequency accuracy of the mas- out, noise generation, noise tolerance, transient response and holdover ter clock determines the frequency accuracy of the DPLLs in Free-Run performance. The T4 DPLL provides rate conversion functions that can mode. The frequency stability of the master clock determines the fre- be used, for example, to convert a recovered line clock to a 1.544 MHz, quency stability of the DPLLs in Free-Run mode and in Holdover mode. 2.048MHz or 64 kHz synchronization reference for external equipment. The T0 DPLL can be configured with a range of selectable filtering The 82V3910 provides ten single ended reference inputs and two dif- bandwidths from 0.5 mHz to 35 Hz. The 15 mHz and lower bandwidths ferential reference inputs that can operate at common Ethernet, SONET/ can be used to lock the T0 DPLL directly to a 1 pulse per second (PPS) SDH and PDH frequencies and other frequencies. The device also pro- reference. The 0.1 Hz bandwidth can be used for G.8262/G.813 Option vides two Alternate Mark Inversion (AMI) inputs for Composite Clock 2 or Telcordia GR-253-CORE S3 or SMC applications. The bandwidths (CC) signals bearing 64 kHz, 8 kHz and 0.4 kHz synchronization infor- in the range 1.2 Hz to 8 Hz can be used for G.8262/G.813 Option 1 mation. The references are continually monitored for loss of signal and applications. The bandwidths 18 Hz and 35 Hz can be used in jitter for frequency offset per user programmed thresholds. All of the refer- attenuation and rate conversion applications. ences are available to both digital PLLs (DPLLs). The active reference The T4 DPLL can be configured with filtering bandwidths of 18Hz or for each DPLL is determined by forced selection or by automatic selec- 35 Hz. tion based on user programmed priorities and locking allowances and The clocks synthesized by the 82V3910 DPLLs can be passed based on the reference monitors. through either of the two independent voltage controlled crystal oscillator The 82V3910 can accept a clock reference and a phase locked (VCXO) based jitter attenuating analog PLLs (APLLs). Both APLLs drive external sync signal as a pair. The T0 DPLL can lock to the reference two independent dividers that have differential outputs. The APLLs use clock input and align its frame sync and multi-frame sync outputs with external crystal resonators with resonant frequencies equal to the APLL the paired external sync input. The device provides to two external sync base frequency divided by 25. Both APLLs can be provisioned with one inputs that can be associated with any of the twelve reference inputs to or two selectable crystal resonators to support up to two base frequen- create up to two pairs. The external sync signals can have a frequency cies per APLL. The output clocks generated by the APLLs exhibit jitter of 1 Hz, 2 kHz or 8 kHz. This feature enables the T0 DPLL to phase below 0.30ps RMS over the integration range 10 kHz to 20 MHz for most align its frame sync and multi-frame sync outputs with an external sync output frequencies. input without the need use a low bandwidth setting to lock directly to an Any of the 82V3910 DPLL clocks can be routed through a mux to any external sync input. of five single ended outputs via independent output dividers. The output Both DPLLs support four primary operating modes: Free-Run, of the T0 DPLL can be routed through the two auto-dividers to the single Locked, Holdover and Digitally Controlled Oscillator (DCO) Control. In ended frame sync output that operates at 8 kHz or 1 PPS, Free-Run mode the DPLLs generate clocks based on the master clock Description 2 July 1, 2013