Synchronous Ethernet Two-Channel IDT82V3911 Short Form PLL for 10GbE and 40GbE Datasheet Supports Forced or Automatic operating mode switch controlled by FEATURES an internal state machine. Automatic mode switch supports Free- HIGHLIGHTS Run, Locked and Holdover modes Jitter generation <0.3 ps RMS (10 kHz to 20 MHz), meets jitter Supports manual and automatic selected input clock switch requirements of leading PHYs supporting 10GBASE-R, 10GBASE- Supports automatic hitless selected input clock switch on clock fail- W, 40GBASE-R, OC-192 and STM-64 ure Supports ITU-TG.8261/G.8262 Synchronous Ethernet (SyncE) Supports three types of input clock sources: recovered clock from compliant equipment STM-N or OC-n, PDH network synchronization timing and external Supports clock generation for IEEE-1588 applications synchronization reference timing Generates SyncE interface clocks (1GE, 10GE, and 40GE) Supports LVPECL/LVDS and CMOS input/output technologies Supports master clock calibration MAIN FEATURES Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE, Provides an integrated solution for reference switching, frequency ITU-T G.812, ITU-T G.8262, ITU-T G.813 and ITU-T G.783 Recom- translation and jitter attenuation for SyncE and SONET/SDH inter- mendations faces Integrates 2 DPLLs, one for the transmit path and one for the OTHER FEATURES receive path I2C Microprocessor interface Selectable DPLL bandwidth: 18 Hz and 35 Hz IEEE 1149.1 JTAG Boundary Scan Integrates 2 jitter attenuating APLLs to generate ultra-low jitter Single 3.3 V operation with 5 V tolerant CMOS I/Os clocks 1mm ball pitch CABGA green package Supports 3 clock modes: SONET, Ethernet, and Ethernet LAN- APPLICATIONS PHY Core and access IP switches / routers Supports up to two crystal connections, allowing each APLL to Gigabit and Terabit IP switches / routers support up to two modes of operation Central Office Timing Source and Distribution Supports input and output clocks covering a wide range of frequen- DWDM cross-connect and transmission equipment cies IP core routers and access equipment Provides IN3, IN4, IN7,IN6 input CMOS clocks whose frequen- Cellular and WLL base-station node clocks cies range from 2 kHz to 156.25 MHz Broadband and multi-service access equipment Provides IN1 and IN2 input differential clocks whose frequencies range from 2 kHz to 625 MHz Provides OUT1 to OUT5 output CMOS clocks whose frequency range from 1PPS to 125 MHz Provides OUT6~OUT9 output differential clocks whose fre- quency range from 25 MHz to 644.53125 MHz Provides a 1PPS, 2 kHz, 4 kHz, or 8 kHz frame sync input signal, and a 1PPS, 2 kHz or 8 kHz frame sync output signal IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 July 1, 2013 DSC-7238/-IDT82V3911 SHORT FORM DATASHEET SYNCHRONOUS ETHERNET TWO-CHANNEL PLL FOR 10GBE AND 40GBE DESCRIPTION The 82V3911 Synchronous Ethernet (SyncE) Two-channel PLL is a The 82V3911 provides four single ended reference inputs and two jitter attenuating device with rate conversion and reference switching differential reference inputs that can operate at common Ethernet, capabilities its ultra-low jitter output clocks are used to directly synchro- SONET/SDH and PDH frequencies and other frequencies. The refer- nize 10GBASE-R/10GBASE-W and OC-192/STM-64 PHYs and ences are continually monitored for loss of signal and for frequency off- 40GBASE-R PHYs in Synchronous Ethernet and SONET/SDH equip- set per user programmed thresholds. All of the references are available ment. When the 82V3911 is locked to a Synchronous Equipment Timing to both DPLLs. The active reference for each DPLL is determined by Source (SETS) that meets the requirements of ITU-T G.8262, G.813 or forced selection or by automatic selection based on user programmed Telcordia GR-253-CORE Stratum 3 or SONET Minimum Clock the priorities and locking allowances and based on the reference monitors. clocks generated by the 82V3911 will also meet those requirements. The 82V3911 can accept a clock reference and a phase locked The two 82V3911 timing channels are defined by independent Digital external sync signal as a pair. DPLL1 can lock to the reference clock PLLs (DPLLs) with embedded clock synthesizers. The two independent input and align its frame sync and multi-frame sync outputs with the timing channels allow the 82V3911 to synchronize transmit interfaces paired external sync input. The device provides to two external sync with the selected system backplane clock, and to simultaneously provide inputs that can be associated with any of the six reference inputs to cre- a recovered clock from a selected receive interface to the system back- ate up to two pairs. The external sync signals can have a frequency of 1 plane. DPLL1 is preferred for synchronizing transmit interfaces because Hz, 2 kHz or 8 kHz. This feature enables DPLL1 to phase align its frame it has the more sophisticated holdover mode. sync and multi-frame sync outputs with an external sync input without the need use a low bandwidth setting to lock directly to an external sync Both DPLLs support three primary operating modes: Free-Run, input. Locked and Holdover. In Free-Run mode the DPLLs generate clocks based on the master clock alone. In Locked mode the DPLLs filter refer- The clocks synthesized by the 82V3911 DPLLs can be passed ence clock jitter with one of the following selectable bandwidths: 18 Hz through either of the two independent voltage controlled crystal oscillator or 35 Hz. In Locked mode the long-term DPLL frequency accuracy is the (VCXO) based jitter attenuating analog PLLs (APLLs). Both APLLs drive same as the long term frequency accuracy of the selected input refer- two independent dividers that have differential outputs. The APLLs use ence. In Holdover mode the DPLL uses frequency data acquired while in external crystal resonators with resonant frequencies equal to the APLL Locked mode to generate accurate frequencies when input references base frequency divided by 25. Both APLLs can be provisioned with one are not available. or two selectable crystal resonators to support up to two base frequen- cies per APLL. The output clocks generated by the APLLs exhibit jitter The 82V3911 requires a 12.8 MHz master clock for its reference below 0.30ps RMS over the integration range 10 kHz to 20 MHz for most monitors and other digital circuitry. The frequency accuracy of the mas- output frequencies. ter clock determines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the master clock determines the fre- quency stability of the DPLLs in Free-Run mode and in Holdover mode. Description 2 July 1, 2013