830154AMI-08LF Renesas

Over-Voltage Tolerant 1.5V, 1:4 830154I-08 Fanout Buffer Data Sheet General Description Features Low-skew 1:4 fanout buffer The 830154I-08 is an LVCMOS, over-voltage tolerant clock fanout buffer targeted for clock generation in high-performance Supports 3.3V, 2.5V, 1.8V and 1.5V power supplies telecommunication, networking and computing applications. The LVCMOS input and output levels device is optimized for low-skew clock distribution in low-voltage 3.6V Over-voltage tolerance at the clock and control inputs applications. The input over-voltage tolerance enables using this Supports clock frequencies up to 160MHz device in mixed-mode voltage applications. An output enable pin LVCMOS compatible control input for output disable controls whether the outputs are in the active or high impedance Output disabled to a high-impedance state state. Guaranteed output skew characteristics make the 830154I-08 -40C to 85C ambient operating temperature ideal for those applications demanding well defined performance and Available in lead-free RoHS 6 packages (8-TSSOP, 8-SOIC) repeatability. The 830154I-08 is packaged in a small 8-TSSOP and in an 8-SOIC package. Block Diagram Pulldown Q1 CLK IN Pin Assignments Q2 CLK IN OE 1 8 Q1 V 2 7 DD Q3 Q2 GND 3 6 Q3 Q4 4 5 Q4 830154AMI-08 Pullup 8-SOIC, 150 mil OE 3.9mm x 4.9mm x 1.375mm package body M-Package Top View 830154AGI-08 8-TSSOP 4.4mm x 3.0mm x 0.925mm package body G-Package Top View 2016 Integrated Device Technology, Inc 1 Revision A March 30, 2016830154I-08 Data Sheet Table 1. Pin Descriptions Number Name Type Description 1 CLK IN Input Pulldown Single-ended clock input. LVCMOS interface levels. 2 Q1 Output Single-ended clock output. LVCMOS interface levels. 3 Q2 Output Single-ended clock output. LVCMOS interface levels. 4 Q3 Output Single-ended clock output. LVCMOS interface levels. 5 Q4 Output Single-ended clock output. LVCMOS interface levels. 6 GND Power Power supply ground. 7V Power Power supply pin. DD 8 OE Input Pullup Output enable pin. See Table 3. LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN = 3.465V 14 pF V DD V = 2.375V 13 pF DD C Power Dissipation Capacitance PD V = 1.95V 13 pF DD = 1.6V 12 pF V DD R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.3V 5% 9 DD V = 2.5V 5% 10 DD R Output Impedance OUT V = 1.8V 0.15V 12 DD V = 1.5 0.1V 15 DD Function Table Table 3. OE Configuration Table Input OE Operation 0 Q 4:1 disabled (high-impedance) 1 (default) Q 4:1 enabled NOTE: OE is an asynchronous control. 2016 Integrated Device Technology, Inc 2 Revision A March 30, 2016