OE 2-Bit, 2:1, Single-Ended Multiplexer 83052I-01 Datasheet General Description Features The 83052I-01 is a 2-bit, 2:1, Single-ended Multiplexer and a 2-bit, 2:1 single-ended multiplexer member of the family of High Performance Clock Solutions from Nominal output impedance: 15 (V = 3.3V) DDO IDT. The 83052I-01 has two selectable single-ended clock inputs Maximum output frequency: 250MHz and two single-ended clock outputs. The output has a V pin DDO Propagation delay: 3ns (maximum), V = V = 3.3V which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for DD DDO use in voltage translation applications. An output enable pin Input skew: 85ps (maximum), V = V = 3.3V DD DDO places the output in a high impedance state which may be useful Part-to-part skew: 500ps (maximum), V = V = 3.3V DD DDO for testing or debug. Possible applications include systems with up Output skew: 65ps (maximum), V = V = 3.3V DD DDO to two transceivers which need to be independently set for Additive phase jitter, RMS (12KHz - 20MHz): different rates. For example, a board may have two transceivers, 0.15ps (typical) each of which need to be independently configured for 1 Gigabit Ethernet or 1 Gigabit Fibre Channel rates. Another possible Operating supply modes: application may require the ports to be independently set for FEC V /V DD DDO (Forward Error Correction) or non-FEC rates. The device operates 3.3V/3.3V up to 250MHz and is packaged in a 16 TSSOP. 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram Pulldown SEL0 nc nc 1 16 15 2 VDDO VDDO nc 14 nc 3 Pulldown CLK0 0 13 GND GND 4 12 Q1 Q0 5 Q0 11 SEL1 6 SEL0 Pulldown CLK1 10 1 CLK1 7 CLK0 9 VDD 8 83052I-01 0 16-Lead TSSOP Q1 4.4mm x 5.0mm x 0.925mm package body 1 G Package Pulldown SEL1 Pullup OE 2015 Integrated Device Technology, Inc 1 December 16, 201583052I-01 Datasheet Table 1. Pin Descriptions Number Name Type Description 1, 3, 14, 16 nc Unused No connect. 2, 15 V Power Output supply pins. DDO 4, 13 GND Power Power supply ground 5, 12 Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. Clock select inputs. See Table 3, Control Input Function Table. 6, 11 SEL1, SEL0 Input Pulldown LVCMOS / LVTTL interface levels. 7, 10 CLK1, CLK0 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 8V Power Power supply pin. DD Output enable. When LOW, outputs are in HIGH impedance state. When 9 OE Input Pullup HIGH, outputs are active. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 18 pF DDO Power Dissipation Capacitance C V = 2.625V 19 pF PD DDO (per output) NOTE 1 = 2.0V 19 pF V DDO V = 3.465V 15 DDO R Output Impedance V = 2.625V 17 OUT DDO V = 2.0V 25 DDO Function Tables Table 3. Control Input Function Table Control Inputs Outputs SEL1 SEL0 Q0 Q1 0 0 CLK0 (default) CLK0 0 1 CLK1 CLK0 1 0 CLK0 CLK1 1 1 CLK1 CLK1 2015 Integrated Device Technology, Inc 2 December 16, 2015