2:1, Single-Ended Multiplexer 83052I Data Sheet GENERAL DESCRIPTION FEATURES The 83052I is a low skew, 2:1, Single-ended Multiplexer. The 83052I 2:1 single-ended multiplexer has two selectable single-ended clock inputs and one single-ended Q nominal output impedance: 15 (V = 3.3V) DDO clock output. The output has a V pin which may be set at 3.3V, DDO 2.5V, or 1.8V, making the device ideal for use in voltage trans-lation Maximum output frequency: 250MHz applications. An output enable pin places the output in a high im- Propagation delay: 2.7ns (maximum), (V = V = 3.3V) DD DDO pedance state which may be useful for testing or debug. The device operates up to 250MHz and is packaged in an 8 TSSOP. Input skew: 160ps (maximum), (V = V = 3.3V) DD DDO Part-to-part skew: 490ps (maximum), (V = V = 3.3V) DD DDO Additive phase jitter, RMS at 155.52MHz (12kHz - 20MHz): 0.18ps (typical), (V = V = 3.3V) DD DDO Operating supply modes: V /V DD DDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT CLK0 VDDO Q 1 8 GND SEL0 2 7 CLK1 CLK0 3 6 CLK1 Q VDD 4 5 OE SEL0 83052I OE 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View 2015 Integrated Device Technology, Inc 1 December 15, 201583052I Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1V Power Output supply pin. DDO 2 GND Power Power supply ground. 3, 6 CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 4V Power Positive supply pin. DD Output enable. When LOW, outputs are in HIGH impedance state. 5 OE Input Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Clock select input. See Table 3. Control Input Function Table. 7 SEL0 Input Pulldown LVCMOS / LVTTL interface levels. 8 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 18 pF DDO Power Dissipation Capacitance C V = 2.625V 19 pF PD DDO (per output) V = 1.89V 19 pF DDO R Output Impedance 15 OUT TABLE 3. CONTROL INPUT FUNCTION TABLE Control Inputs Input Selected to Q SEL0 0 CLK0 1 CLK1 2015 Integrated Device Technology, Inc 2 December 15, 2015