4-Bit, 2:1, Single-Ended Multiplexer 83054I-01 Datasheet GENERAL DESCRIPTION FEATURES The 83054I-01 is a 4-bit, 2:1, Single-ended Multiplexer and a Four-bit, 2:1 single-ended multiplexer member of the family of High Performance Clock Solutions from Nominal output impedance: 15 (V = 3.3V) DDO IDT. The 83054I-01 has two selectable single-ended clock inputs and four single-ended clock outputs. The output has a V pin Maximum output frequency: 250MHz DDO which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal Propagation delay: 3.2ns (maximum), V = V = 3.3V DD DDO for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful Input skew: 170ps (maximum), V = V = 3.3V DD DDO for testing or debug. Possible applications include systems with up Output skew: 90ps (maximum), V = V = 3.3V to four transceivers which need to be independently set for different DD DDO rates. For example, a board may have four transceivers, each of Part-to-part skew: 800ps (maximum), V = V = 3.3V DD DDO which need to be independently con gured for 1 Gigabit Ethernet Additive phase jitter, RMS at 155.52MHz, (12kHz 20MHz): or 1 Gigabit Fibre Channel rates. Another possible application may 0.18ps (typical) require the ports to be independently set for FEC (Forward Error Correction) or non-FEC rates. The device operates up to 250MHz Operating supply modes: and is packaged in a 16 TSSOP. V /V DD DDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT Pulldown SEL0 SEL3 1 16 SEL0 Q3 2 15 Q0 Pulldown VDDO 3 14 VDDO CLK0 0 GND 4 13 GND Q0 Q2 5 12 Q1 Pulldown SEL2 6 11 SEL1 CLK1 1 CLK1 7 10 CLK0 VDD 8 9 OE 83054I-01 0 16-Lead TSSOP Q3 4.4mm x 5.0mm x 0.92mm package body 1 G Package Top View Pulldown SEL3 OE Pullup 2015 Integrated Device Technology, Inc 1 December 15, 201583054I-01 Datasheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 6 SEL3, SEL2, Clock select inputs. See Control Input Function Table. Input Pulldown 11, 16 SEL1, SEL0 LVCMOS / LVTTL interface levels. 2, 5, 12, 15 Q3, Q2, Q1, Q0 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 3, 14 V Power Output supply pins. DDO 4, 13 GND Power Power supply ground. 7, 10 CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 8V Power Positive supply pin. DD Output enable. When LOW, outputs are in HIGH impedance state. 9 OE Input Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Units Symbol Parameter Test Conditions Minimum Typical Maximum C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 18 pF DDO Power Dissipation Capacitance C V = 2.625V 19 pF PD DDO (per output) V = 2.0V 19 pF DDO V = 3.465V 15 DDO R Output Impedance V = 2.625V 17 OUT DDO V = 2.0V 25 DDO TABLE 3. CONTROL INPUT FUNCTION TABLE Control Inputs Outputs SELx Qx 0 CLK0 1 CLK1 2015 Integrated Device Technology, Inc 2 December 15, 2015