4:1, Single-Ended Multiplexer 83054 Data Sheet GENERAL DESCRIPTION FEATURES The 83054 is a low skew, 4:1, Single-ended Multiplexer and a 4:1 single-ended multiplexer member of the family of High Performance Clock Solutions from IDT. Q nominal output impedance: 7 (V = 3.3V) DDO The 83054 has four selectable single-ended clock inputs and one single-ended clock output. The output has a V pin which may be Maximum output frequency: 250MHz DDO set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage Propagation delay: 3ns (maximum), V = V = 3.3V DD DDO translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or Input skew: 225ps (maximum), V = V = 3.3V DD DDO debug purposes. The device operates up to 250MHz and is pack- Part-to-part skew: 780ps (maximum), V = V = 3.3V aged in a 16 TSSOP package. DD DDO Additive phase jitter, RMS: 0.19ps (typical), 3.3V/3.3V Operating supply modes: V /V DD DDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT CLK0 CLK1 Q CLK2 CLK3 83054 16-Lead TSSOP SEL1 4.4mm x 5.0mm x 0.92mm package body SEL0 G Package OE Top View 2015 Integrated Device Technology, Inc 1 December 15, 201583054 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. Output enable. When LOW, outputs are in HIGH impedance state. 3 OE Input Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. 4, 8, CLK3, CLK2, Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 10, 14 CLK1, CLK0 5 GND Power Power supply ground. Clock select input. See Control Input Function Table. 7, 9 SEL1, SEL0 Input Pulldown LVCMOS / LVTTL interface levels. 2, 6, 11, 13, 15 nc Unused No connect. 12 V Power Power and input supply pin. DD 16 V Power Output supply pin. DDO NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN VDDO = 3.465V 18 pF Power Dissipation Capacitance C VDDO = 2.625V 20 pF PD (per output) VDDO = 1.89V 30 pF VDDO = 3.465V 7 R Output Impedance VDDO = 2.625V 7 OUT VDDO = 1.89V 10 TABLE 3. CONTROL INPUT FUNCTION TABLE Control Inputs Input Selected to Q SEL1 SEL0 0 0 CLK0 0 1 CLK1 1 0 CLK2 1 1 CLK3 2015 Integrated Device Technology, Inc 2 December 15, 2015