OE 6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER ICS83056I-01 General Description Features The ICS83056I-01 is a 6-bit, 2:1, Single-ended 6-Bit, 2:1 single-ended LVCMOS multiplexer ICS LVCMOS Multiplexer and a member of the Maximum output frequency: 250MHz HiPerClockS HiPerClockS family of High Performance Clock Additive phase jitter, RMS at 155.52MHz (12kHz - 20MHz): Solutions from IDT. The ICS83056I-01 has two 0.18ps (typical) selectable single-ended LVCMOS clock inputs and Operating supply modes: six single-ended LVCMOS clock outputs. The outputs have a V DDO Core/Output which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin V /V DD DDO places the output in a high impedance state which may be useful 3.3V/3.3V for testing or debug. Possible applications include systems with up 3.3V/2.5V to 6 transceivers which need to be independently set for different 3.3V/1.8V rates. For example, a board may have six transceivers, each of 2.5V/2.5V which need to be independently configured for 1 Gigabit Ethernet 2.5V/1.8V or 1 Gigabit Fibre Channel rates. Another possible application may require the ports to be independently set for FEC (Forward Error -40C to 85C ambient operating temperature Correction) or non-FEC rates. The device operates up to 250MHz Available in both standard (RoHS 5) and lead-free (RoHS 6) and is packaged in a 20 TSSOP. packages Block Diagram Pulldown CLK0 0 Q0 Pulldown CLK1 1 Pulldown SEL0 0 Q1 Pin Assignment 1 SEL0 SEL5 1 20 Pulldown SEL1 2 19 Q0 Q5 V DDO 3 18 VDDO GND 4 17 GND 0 Q4 5 16 Q1 Q2 SEL4 6 15 SEL1 CLK1 7 14 CLK0 1 V 8 13 DD Pulldown SEL2 Q3 9 12 Q2 SEL3 10 11 SEL2 0 ICS83056I-01 Q3 20-Lead TSSOP 1 6.50mm x 4.40mm x 0.925mm Pulldown SEL3 package body G Package 0 Top View Q4 1 Pulldown SEL4 0 Q5 1 Pulldown SEL5 Pullup OE IDT / ICS 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER 1 ICS83056AGI-01 REV. A JANUARY 29, 2009ICS83056I-01 6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER Table 1. Pin Descriptions Number Name Type Description 1, 6 SEL5, SEL4, 10, 11 SEL3, SEL2, Input Pulldown Clock select inputs. See Table 3. LVCMOS / LVTTL interface levels. 15, 20 SEL1, SEL0 2, 5, 9 Q5, Q4, Q3, Output Single-ended clock output. LVCMOS/LVTTL interface levels. 12, 16, 19 Q2, Q1, Q0 3, 18 V Power Output supply pins. DDO 4, 17 GND Power Power supply ground. 7, 14 CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 8V Power Power supply pin. DD Output enable. When LOW, outputs are in a High impedance state. 13 OE Input Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN V = V = 3.465V 18 pF DD DDO Power Dissipation Capacitance C V = V = 2.625V 19 pF PD DD DDO (per output) V = V = 2V 19 pF DD DDO R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 15 DDO R Output Impedance V = 2.625V 17 OUT DDO V = 2V 25 DDO Function Tables Table 3. Control Input Function Table Control Inputs Outputs SELx Qx 0CLK0 1CLK1 IDT / ICS 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER 2 ICS83056AGI-01 REV. A JANUARY 29, 2009