8:1, Single-Ended Multiplexer 83058 Datasheet GENERAL DESCRIPTION FEATURES The 83058I is a low skew, 8:1, Single-ended Multiplexer 8:1 single-ended multiplexer and a member of the family of High Performance Clock Solutions from IDT. The 83058I has eight selectable single- Q nominal output impedance: 7 (V = 3.3V) DDO ended clock inputs and one single-ended clock output. The Maximum output frequency: 250MHz output has a V pin which may be set at 3.3V, 2.5V, or DDO 1.8V, making the device ideal for use in voltage transla- Propagation delay: 3ns (maximum), V = V = 3.3V tion applications. An output enable pin places the output in DD DDO a high impedance state which may be useful for testing or Input skew: 225ps (maximum), V = V = 3.3V debug purposes. The device operates up to 250MHz and is pack- DD DDO aged in a 16 TSSOP package. Part-to-part skew: 475ps (maximum), V = V = 3.3V DD DDO Additive phase jitter, RMS: 0.19ps (typical), 3.3V/3.3V Operating supply modes: V /V DD DDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT 1 16 Q VDDO CLK0 2 15 CLK7 CLK0 3 14 OE SEL0 CLK1 4 13 CLK6 CLK1 5 12 GND VDD CLK2 6 11 CLK5 CLK2 7 10 SEL2 SEL1 Q 8 9 CLK3 CLK4 CLK3 CLK4 83058I 16-Lead TSSOP CLK5 4.4mm x 5.0mm x 0.92mm package body G Package CLK6 Top View CLK7 SEL2 SEL1 SEL0 OE 2015 Integrated Device Technology, Inc 1 December 15, 201583058 Datasheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. 2, 4, 6, 8, CLK7, CLK6, CLK5, 9, 11, CLK4, CLK3, CLK2, Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 13, 15 CLK1, CLK0 Output enable. When LOW, outputs are in HIGH impedance state. 3 OE Input Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. 5 GND Power Power supply ground. Clock select input. See Control Input Function Table. 7, 10, 14 SEL2, SEL1, SEL0 Input Pulldown LVCMOS / LVTTL interface levels. 12 V Power Core and input supply pin. DD 16 V Power Output supply pin. DDO NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 18 pF DDO Power Dissipation Capacitance V = 2.625V 20 pF C PD DDO (per output) V = 1.89V 30 pF DDO V = 3.465V 7 DDO R Output Impedance V = 2.625V 7 OUT DDO V = 1.89V 10 DDO TABLE 3. CONTROL INPUT FUNCTION TABLE Control Inputs Input Selected to Q SEL2 SEL1 SEL0 0 0 0 CLK0 0 0 1 CLK1 0 1 0 CLK2 0 1 1 CLK3 1 0 0 CLK4 1 0 1 CLK5 1 1 0 CLK6 1 1 1 CLK7 2015 Integrated Device Technology, Inc 2 December 15, 2015