ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-to- 4 LVCMOS/LVTTL outputs LVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable Selectable differential or LVCMOS/LVTTL clock inputs clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to CLK, nCLK pair can accept the following differential eliminate runt pulses on the outputs during asynchronous input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL assertion/deassertion of the clock enable pin. Outputs are LVCMOS CLK supports the following input types: forced LOW when the clock is disabled. A separate output LVCMOS, LVTTL enable pin controls whether the outputs are in the active or high impedance state. Maximum output frequency: 350MHz Guaranteed output and part-to-part skew characteristics make Output skew: 40ps (maximum) the ICS8305I ideal for those applications demanding well de- Part-to-part skew: 700ps (maximum) fined performance and repeatability. Additive phase jitter, RMS: 0.04ps (typical) 3.3V core, 3.3V, 2.5V or 1.8V output operating supply -40C to 85C ambient operating temperature Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT 1 CLK EN GND 16 Q0 D 2 OE 15 VDDO Q VDD 3 14 Q1 LE 4 CLK EN 13 GND LVCMOS CLK 0 0 5 CLK 12 Q2 Q0 6 CLK nCLK 11 VDDO 1 1 7 nCLK CLK SEL 10 Q3 LVCMOS CLK 8 9 GND Q1 CLK SEL ICS8305I Q2 16-Lead TSSOP 4.4mm x 3.0mm x 0.92mm package body Q3 G Package Top View OE 8305AGI REV. B SEPTEMBER 17, 2012 1ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS NeumberNeam Tnyp Descriptio 1D, 9, 13 GrNP.owe Power supply ground Output enable. When LOW, outputs are in HIGH impedance state. 2EOtIpnpu Pullu When HIGH, outputs are active. LVCMOS / LVTTL interface levels. 3VP.ower Core supply pin DD Synchronizing clock enable. When LOW, the output clocks are 4NCtLK E Ipnpu Pullu disabled. When HIGH, output clocks are enabled. LVCMOS / LVTTL interface levels. 5KCtL InnpuP.ulldow Non-inverting differential clock input Pullup/ 6KntCL Inpu Inverting differential clock input. V /2 default when left floating. DD Pulldown Clock select input. When HIGH, selects CLK, nCLK inputs. 7LCtLK SE Ipnpu Pullu When LOW, selects LVCMOS CLK input. LVCMOS / LVTTL interface levels. 8KLtVCMOS CLInnpuP.ulldow LVCMOS / LVTTL clock input 100, 12, 14, 16Qt3, Q2, Q1, QO.utpu Clock outputs. LVCMOS / LVTTL interface levels 1V1, 15 P.ower Output supply pins DDO NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS SrymbolPsaramete Tmest Condition MlinimuTmypica Maximu Units C Input Capacitance 4Fp IN R Input Pullup Resistor 5k1 PULLUP R Input Pulldown Resistor 5k1 PULLDOWN Power Dissipation Capacitance C 1F1 p PD (per output) R Output Impedance 57 12 OUT 8305AGI REV. B SEPTEMBER 17, 2012 2