GND ICS8305 Low Skew, 1-to-4 Multiplexed Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer DATA SHEET General Description Features The ICS8305 is a low skew, 1-to-4, Differential/ LVCMOS-to- Four LVCMOS / LVTTL outputs, 7 output impedance LVCMOS/LVTTL Fanout Buffer. The ICS8305 has selectable clock Selectable differential or LVCMOS / LVTTL clock inputs inputs that accept either differential or single ended input levels. The CLK, nCLK pair can accept the following differential input levels: clock enable is internally synchronized to eliminate runt pulses on LVPECL, LVDS, LVHSTL, HCSL, SSTL the outputs during asynchronous assertion/deassertion of the clock LVCMOS CLK supports the following input types: LVCMOS, enable pin. Outputs are forced LOW when the clock is disabled. A LVTTL separate output enable pin controls whether the outputs are in the Maximum output frequency: 350MHz active or high impedance state. Output skew: 35ps (maximum) Guaranteed output and part-to-part skew characteristics make the ICS8305 ideal for those applications demanding well defined Part-to-part skew: 700ps (maximum) performance and repeatability. Additive phase jitter, RMS: 0.04ps (typical) Power supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 3.3V/1.5V 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pullup CLK EN GND 1 16 Q0 D 15 Q OE 2 VDDO 14 LE VDD Q1 3 Pulldown 13 LVCMOS CLK CLK EN 4 GND 0 0 12 CLK 5 Q2 Q0 Pulldown CLK 11 1 nCLK 6 VDDO 1 Pullup/ nCLK 10 7 Pulldown CLK SEL Q3 9 Q1 8 LVCMOS CLK Pullup CLK SEL Q2 ICS8305 16-Lead TSSOP Q3 4.4mm x 3.0mm x 0.925mm package body Pullup OE G Package Top View ICS8305AG REVISION C MAY 30, 2014 1 2014 Integrated Device Technology, Inc.ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 9, 13 GND Power Power supply ground Output enable. When LOW, outputs are in HIGH impedance state. 2 OE Input Pullup When HIGH, outputs are active. LVCMOS/LVTTL interface levels. 3V Power Power supply pin. DD Synchronizing clock enable. When LOW, the output clocks are disabled. 4 CLK EN Input Pullup When HIGH, output clocks are enabled. LVCMOS/LVTTL interface levels. 5 CLK Input Pulldown Non-inverting differential clock input. Pullup/ 6 nCLK Input Inverting differential clock input. VDD/2 default when left floating. Pulldown Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW, 7 CLK SEL Input Pullup selects LVCMOS CLK input. LVCMOS/LVTTL interface levels. 8 LVCMOS CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Single-ended clock outputs. 7 output impedance. 10, 12, 14, 16 Q3, Q2, Q1, Q0 Output LVCMOS/LVTTL interface levels. Power Output supply pins. 11, 15 V DDO NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Power Dissipation Capacitance C 11 pF PD (per output) Output Impedance 7 R OUT ICS8305AG REVISION C MAY 30, 2014 2 2014 Integrated Device Technology, Inc.