Differential Clock/Data Multiplexer 831724 Datasheet General Description Features 2:1 differential clock/data multiplexer with fanout The 831724 is a high-performance, differential HCSL clock/data multiplexer and fanout buffer. The device is designed for the Two selectable, differential inputs multiplexing and fanout of high-frequency clock and data signals. Each differential input pair can accept the following levels: HCSL, LVDS, LVPECL. The device has two differential, selectable clock/data inputs. The Four differential HCSL outputs selected input signal is distributed to four low-skew differential HCSL outputs. Each input pair accepts HCSL, LVDS and LVPECL levels. Maximum input/output clock frequency: 350MHz The 831724 is characterized to operate from a 3.3V power supply. Maximum input/output data rate: 700Mb/s (NRZ) Guaranteed input, output-to-output and part-to-part skew LVCMOS interface levels for all control inputs characteristics make the 831724 ideal for those clock and data PCI Express Gen 1,2,3 jitter compliant distribution applications demanding well-defined performance and Input skew: 165ps (maximum) repeatability. The 831724 supports the clock multiplexing and Output skew: 175ps (maximum) distribution of PCI Express Generation 1, 2, and 3 clock signals. Part-to-part skew: 450ps (maximum) Full 3.3V supply voltage Available in lead-free (RoHS 6) package -40C to 85C ambient operating temperature Pin Assignment Block Diagram QA 32 31 30 29 28 27 26 25 nQA IREF VDD 1 24 nc QB Pulldown 2 nOED 23 nOEC 0 nQB Pullup/down 3 CLK0 22 nc CLK0 4 Pulldown nCLK0 21 nc QC nCLK0 1 Pullup/down CLK1 5 20 nc nQC nCLK1 6 nc 19 QD nOEA 7 SEL 18 CLK1 nQD VDD 8 nc 17 Pulldown nCLK1 9 10 11 12 13 14 15 16 Pullup Pullup Pullup 831724I Pullup 32-Lead VFQFN 5mm x 5mm x 0.925mm package body SEL K Package Top View 2016 Integrated Device Technology, Inc 1 Revision B November 16, 2016 VDD VDD QA nQD nQA QD GND GND QB nQC nQB QC VDD VDD nOEB IREF831724 Datasheet Table 1. Pin Descriptions Number Name Type Description 1, 8, 9, 15, V Power Positive power supply pins. DD 26, 32 Output enable for the QD output. See Table 3D for function. LVCMOS/LVTTL 2 nOED Input Pullup interface levels. 3 CLK0 Input Pulldown Non-inverting clock/data input 0. 4 nCLK0 Input Pulldown/Pullup Inverting differential clock input 0. V /2 default when left floating. DD 5 CLK1 Input Pulldown Non-inverting clock/data input 1. 6 nCLK1 Input Pulldown/Pullup Inverting differential clock input 1. V /2 default when left floating. DD Output enable for the QA output. See Table 3A for function. LVCMOS/LVTTL 7 nOEA Input Pullup interface levels. 10, 11 QA, nQA Output Differential output pair A. HCSL interface levels. 12, 29 GND Power Power supply ground. 13, 14 QB, nQB Output Differential output pair B. HCSL interface levels. Output enable for the QB output. See Table 3B for function. LVCMOS/LVTTL 16 nOEB Input Pullup interface levels. 17, 19, 20, nc Unused No connect pins. 21, 22, 24 Input select. See Table 3E for function. 18 SEL Input Pulldown LVCMOS/LVTTL interface levels. Output enable for the QC output. See Table 3C for function. LVCMOS/LVTTL 23 nOEC Input Pullup interface levels. An external fixed precision resistor (475 ) from this pin to ground provides a 25 IREF Input reference current used for the differential current-mode QX, nQX outputs. 27, 28 QC, nQC Output Differential output pair C. HCSL interface levels. 30, 31 QD, nQD Output Differential output pair D. HCSL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc 2 Revision B November 16, 2016