QA nOEA 4:2 Differential Clock/Data 831742I Datasheet Multiplexer Description Features The 831742I is a high-performance, differential HCSL clock/data 4:2 differential clock/data multiplexer with fanout multiplexer and fanout buffer. The device is designed for the Four selectable, differential input pairs multiplexing and fanout of high-frequency clock and data signals. Each differential input pair can accept the following levels: HCSL, The device has four differential, selectable clock/data inputs. The LVDS and LVPECL selected input signal is distributed to two low-skew differential HCSL Two differential HCSL output pairs outputs. Each input pair accepts HCSL, LVDS and LVPECL levels. Maximum input/output clock frequency: 700MHz The 831742I is characterized to operate from a 3.3V power supply. Maximum input/output data rate: 1400Mb/s (NRZ) Guaranteed input, output-to-output and part-to-part skew LVCMOS interface levels for all control inputs characteristics make the 831742I ideal for those clock and data PCI Express (2.5Gb/s), Gen2 (5 Gb/s), Gen3 (8 Gb/s) and Gen4 (16 distribution applications demanding well-defined performance and Gb/s) clock jitter compliant repeatability. The 831742I supports the clock multiplexing and Input skew: 110ps max distribution of PCI Express (2.5Gb/s), Gen2 (5Gb/s), Gen3 (8Gb/s) and Gen4 (16Gb/s) clock signals. Part-to-part skew: 225ps max Full 3.3V supply voltage Available in lead-free (RoHS 6) -40C to 85C ambient operating temperature Block Diagram IREF Pin Assignment CLK0 Pulldown 1 24 SEL1 GND 0 0 Pullup/down 2 23 IREF CLK0 nCLK0 3 22 SEL0 nCLK0 V 4 21 VDD Pulldown DD CLK1 QA 0 1 5 20 nQB CLK1 Pullup/down nQA nCLK1 6 19 QB nCLK1 nQA CLK2 7 18 Pulldown CLK 1 0 Q % 8 17 nCLK2 Pullup/down GND 9 16 VDD nCLK nQ % CLK3 GND 10 15 1 1 nCLK3 nOEB Pulldown 11 14 CLK3 V 12 13 DD Pullup/down nCLK3 831742AGI Pulldown 6(/ 24-Lead TSSOP Pulldown 6(/ 4.4mm x 7.8mm x 0.925mm package body G Package Pullup Top View nOEA Pullup Q2(% 2021 Renesas Electronics Corporation 1 R31DS0073EU0200 July 30, 2021831742I Datasheet Table 1. Pin Descriptions Number Name Type Description 1, 9, 15 GND Power Power supply ground. 2 CLK0 Input Pulldown Non-inverting clock/data input. 3 nCLK0 Input Pulldown/Pullup Inverting differential clock/data input. V /2 default when left floating. DD 4, 12, V Power Positive power supply. DD 16, 21 5 CLK1 Input Pulldown Non-inverting clock/data input. 6 nCLK1 Input Pulldown/Pullup Inverting differential clock/data input. V /2 default when left floating. DD 7 CLK2 Input Pulldown Non-inverting clock/data input. 8 nCLK2 Input Pulldown/Pullup Inverting differential clock/data input. V /2 default when left floating. DD 10 CLK3 Input Pulldown Non-inverting clock/data input. 11 nCLK3 Input Pulldown/Pullup Inverting differential clock/data input. V /2 default when left floating. DD Output enable for the QA output. See Table 3A for function. 13 nOEA Input Pullup LVCMOS/LVTTL interface levels. Output enable for the QB output. See Table 3B for function. 14 nOEB Input Pullup LVCMOS/LVTTL interface levels. 17, 18 QA, nQA Output Differential output pair. HCSL interface levels. 19, 20 QB, nQB Output Differential output pair. HCSL interface levels. Differential clock/data Input select. See Table 3C for function. 22, 24 SEL0, SEL1 Input Pulldown LVCMOS/LVTTL interface levels. An external fixed precision resistor (475) from this pin to ground provides a 23 IREF Input reference current used for the differential current-mode QX, nQX outputs. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2021 Renesas Electronics Corporation 2 R31DS0073EU0200 July 30, 2021