Clock Switch for ATCA/AMC and PCIe 831752 Applications Data Sheet General Description Features The 831752 is a high-performance, differential HCSL clock switch. Clock switch for PCIe and ATCA/AMC applications The device is designed for the routing of PCIe clock signals in Supports local and common ATCA/AMC clock modes ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen Bi-directional clock I/O FCLK: 3. The device has one differential, bi-directional I/O (FCLK) for - When operating as an output, FCLK is a source-terminated connection to ATCA clock sources and to clock receivers through a HCSL signal. - When operating as an input, FCLK accepts HCSL, LVDS and connector. The differential clock input CLK is the local clock input LVPECL levels. and the HCSL output Q is the local clock output. In the common Local clock input (CLK) accepts HCSL, LVDS and LVPECL clock mode, FCLK serves as an input and is routed to the differential differential signals HCSL output Q. There are two local clock modes. In the local clock Local HCSL clock output (Q) mode 0, CLK is the input, Q is the clock output and FCLK is in high-impedance state. In the local clock mode 1, CLK is the input Maximum input/output clock frequency: 500MHz and both Q and FCLK are the outputs of the locally generated PCIe Maximum input/output data rate: 1000Mb/s (NRZ) clock signal. The 831752 is characterized to operate from a 3.3V LVCMOS interface levels for the control inputs power or 2.5V power supply. The 831752 supports the switching of PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) clock compliant signals. Full 3.3V or 2.5V supply voltage Lead-free (RoHS 6) 16-lead TSSOP package Pin Assignment -40C to 85C ambient operating temperature DIR SEL 1 16 IREF nOEFCLK 2 15 GND VDD 3 14 VDD FCLK 4 13 Q nFCLK 5 12 nQ GND 6 11 GND CLK 7 10 VDD nCLK 8 9 nc 831752 16-lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package, Top View Block Diagram 1 FCLK Q nFCLK nQ 22.33 50 50 0 50 50 22.33 1=disable Pulldown CLK Pullup/Pulldown nCLK Pullup nOEFCLK Pulldown DIR SEL IREF 2016 Integrated Device Technology, Inc 1 Revision B June 28, 2016831752 Data Sheet Table 1. Pin Descriptions Number Name Type Description Direction control for the FCLK I/O. Works in conjunction with nOEFCLK. 1 DIR SEL Input Pulldown See Table 3 for function. LVCMOS/LVTTL interface levels. Output enable for the FCLK I/O output. Works in conjunction with 2 nOEFCLK Input Pullup DIR SEL. See Table 3 for function. LVCMOS/LVTTL interface levels. 3, 10, 14 V Power Core and output power supply pin. DD Differential I/O. Signal direction is controlled by DIR SEL. Accepts differential signals when operating as an input. Differential HCSL 4, 5 FCLK, nFCLK I/O signals when operating as an output. Internal source termination can be disabled. See Table 3 for function. 6, 11, 15 GND Power Power supply ground. 7 CLK Input Pulldown Non-inverting input. 8 nCLK Input Pulldown/Pullup Inverting differential clock input. 9 nc Unused No connect. 12, 13 nQ, Q Output Differential output pair. HCSL interface levels. An external fixed precision resistor (475) from this pin to ground 16 IREF Input provides a reference current used for the differential current-mode Q and FCLK outputs. NOTE: Pullup and pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP Function Table Table 3. Direction Control Function Table Input Input DIR SEL nOEFCLK Operation FCLK Function Local clock mode 0. The input signal at CLK is routed to Differential HCSL output with internal 50 source 00 both outputs Q and FCLK. termination Local clock mode 1. The input signal at CLK is routed to Output is disabled (high impedance). Internal 50 0 (default) 1 (default) the output Q. termination is disabled. Differential clock input. Internal 50 source Common reference clock mode. FCLK is the clock input. 1X termination is disabled as well as output driver and Q is the clock output. 22.33 resistors. NOTE: X = 0 or 1 2016 Integrated Device Technology, Inc 2 Revision B June 28, 2016